minor update

hw/rtl/cache/VX_bank.v

@@ -113,7 +113,6 @@ module VX_bank #(
     wire[2:0]            debug_mem_write_st0;
     wire[`REQS_BITS-1:0] debug_tid_st0;
 
-
     wire[31:0]           debug_use_pc_st1e;
     wire[1:0]            debug_wb_st1e;
     wire[4:0]            debug_rd_st1e;
@@ -122,7 +121,6 @@ module VX_bank #(
     wire[2:0]            debug_mem_write_st1e;
     wire[`REQS_BITS-1:0] debug_tid_st1e;
 
-
     wire[31:0]           debug_use_pc_st2;
     wire[1:0]            debug_wb_st2;
     wire[4:0]            debug_rd_st2;
@@ -151,7 +149,7 @@ module VX_bank #(
         .data_out({snrq_addr_st0, snrq_tag_st0}),
         .empty   (snrq_empty),
         .full    (snrq_full),
-        `UNUSED_PIN(size)
+        `UNUSED_PIN (size)
     );
 
     assign snp_req_ready = ~snrq_full;
@@ -174,7 +172,7 @@ module VX_bank #(
         .data_out({dfpq_addr_st0, dfpq_filldata_st0}),
         .empty   (dfpq_empty),
         .full    (dfpq_full),
-        `UNUSED_PIN(size)
+        `UNUSED_PIN (size)
     );
 
     assign dram_fill_rsp_ready = !dfpq_full;
@@ -585,7 +583,7 @@ module VX_bank #(
         .data_out({core_rsp_tid, core_rsp_tag, core_rsp_data}),
         .empty   (cwbq_empty),
         .full    (cwbq_full),
-        `UNUSED_PIN(size)
+        `UNUSED_PIN (size)
     );    
 
     assign core_rsp_valid = !cwbq_empty;
@@ -655,7 +653,7 @@ module VX_bank #(
         .data_out({dwbq_is_dwb_out, dwbq_is_snp_out, dram_wb_req_addr, dram_wb_req_data, snp_rsp_tag}),
         .empty   (dwbq_empty),
         .full    (dwbq_full),
-        `UNUSED_PIN(size)
+        `UNUSED_PIN (size)
     );       
 
     wire dram_wb_req_fire = dram_wb_req_valid && dram_wb_req_ready;

hw/rtl/cache/VX_cache.v

@@ -439,13 +439,13 @@ module VX_cache #(
         .NUM_BANKS         (NUM_BANKS),
         .BANK_LINE_SIZE    (BANK_LINE_SIZE),
         .SNP_REQ_TAG_WIDTH (SNP_REQ_TAG_WIDTH)
-    ) snp_rsp_arb (
+    ) snp_rsp_arb (      
         .per_bank_snp_rsp_valid (per_bank_snp_rsp_valid),
         .per_bank_snp_rsp_tag   (per_bank_snp_rsp_tag),
         .per_bank_snp_rsp_ready (per_bank_snp_rsp_ready),
-        .snp_rsp_valid (snp_rsp_valid),
-        .snp_rsp_tag   (snp_rsp_tag),
-        .snp_rsp_ready (snp_rsp_ready)
+        .snp_rsp_valid          (snp_rsp_valid),
+        .snp_rsp_tag            (snp_rsp_tag),
+        .snp_rsp_ready           (snp_rsp_ready)
     );
     
 endmodule

hw/rtl/cache/VX_cache_dfq_queue.v

@@ -51,7 +51,7 @@ module VX_cache_dfq_queue #(
         .data_out({out_per_bank_dram_fill_req_valid, out_per_bank_dram_fill_req_addr}),
         .empty   (o_empty),
         .full    (dfqq_full),
-        `UNUSED_PIN(size)
+        `UNUSED_PIN (size)
     );
 
     assign use_per_bqual_bank_dram_fill_req_valid = use_empty ? (out_per_bank_dram_fill_req_valid & {NUM_BANKS{!o_empty}}) : (use_per_bank_dram_fill_req_valid & {NUM_BANKS{!use_empty}}); 

hw/rtl/cache/VX_cache_req_queue.v

@@ -84,7 +84,7 @@ module VX_cache_req_queue #(
         .data_out ({out_per_valids, out_per_addr, out_per_writedata, out_per_tag, out_per_mem_read, out_per_mem_write}),
         .empty    (o_empty),
         .full     (reqq_full),
-        `UNUSED_PIN(size)
+        `UNUSED_PIN (size)
     );
 
     wire[NUM_REQUESTS-1:0] real_out_per_valids = out_per_valids & {NUM_REQUESTS{~out_empty}};

hw/rtl/cache/VX_fill_invalidator.v

@@ -10,12 +10,9 @@ module VX_fill_invalidator #(
 ) (
     input  wire     clk,
     input  wire     reset,
-
     input  wire     possible_fill,
     input  wire     success_fill,
-
     input  wire[`LINE_ADDR_WIDTH-1:0] fill_addr,
-
     output reg      invalidate_fill    
 );
 
@@ -23,6 +20,12 @@ module VX_fill_invalidator #(
     
         assign invalidate_fill = 0;
 
+        `UNUSED_VAR (clk)
+        `UNUSED_VAR (reset)
+        `UNUSED_VAR (possible_fill)
+        `UNUSED_VAR (success_fill)
+        `UNUSED_VAR (fill_addr)
+
     end else begin 
 
         reg [FILL_INVALIDAOR_SIZE-1:0]                       fills_active;

hw/rtl/cache/VX_prefetcher.v

@@ -47,7 +47,7 @@ module VX_prefetcher #(
 
         .empty   (current_empty),
         .full    (current_full),
-        `UNUSED_PIN(size)
+        `UNUSED_PIN (size)
     );
 
     assign pref_valid = 0; // TODO use_valid != 0;