rtl refactoring
This commit is contained in:
15
hw/rtl/cache/VX_cache_miss_resrv.v
vendored
15
hw/rtl/cache/VX_cache_miss_resrv.v
vendored
@@ -77,7 +77,7 @@ module VX_cache_miss_resrv #(
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reg [MRVQ_SIZE-1:0] valid_address_match;
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genvar i;
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generate
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generate
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for (i = 0; i < MRVQ_SIZE; i++) begin
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assign valid_address_match[i] = valid_table[i] && (addr_table[i] === fill_addr_st1);
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assign make_ready[i] = is_fill_st1 && valid_address_match[i];
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@@ -143,16 +143,17 @@ module VX_cache_miss_resrv #(
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end
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end
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`ifdef DBG_PRINT_CACHE_MSRQ
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`ifdef DBG_PRINT_CACHE_MSRQ
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integer j;
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always_ff @(posedge clk) begin
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if (mrvq_push || mrvq_pop) begin
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$write("%t: bank%02d:%01d msrq: push=%b pop=%b", $time, CACHE_ID, BANK_ID, mrvq_push, mrvq_pop);
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for (int i = 0; i < MRVQ_SIZE; i++) begin
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if (valid_table[i]) begin
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for (j = 0; j < MRVQ_SIZE; j++) begin
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if (valid_table[j]) begin
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$write(" ");
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if (i == head_ptr) $write("*");
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if (~ready_table[i]) $write("!");
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$write("addr%0d=%0h", i, `LINE_TO_BYTE_ADDR(addr_table[i], BANK_ID));
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if (head_ptr == $bits(head_ptr)'(j)) $write("*");
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if (~ready_table[j]) $write("!");
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$write("addr%0d=%0h", j, `LINE_TO_BYTE_ADDR(addr_table[j], BANK_ID));
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end
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end
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$write("\n");
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