rtl refactoring

2020-05-20 16:59:14 -04:00
parent b5569dd525
commit cefd0d85af
11 changed files with 59 additions and 55 deletions
--- a/hw/rtl/cache/VX_cache_dfq_queue.v
+++ b/hw/rtl/cache/VX_cache_dfq_queue.v
@@ -50,7 +50,8 @@ module VX_cache_dfq_queue #(
        .pop     (pop_qual),
        .data_out({out_per_bank_dram_fill_req_valid, out_per_bank_dram_fill_req_addr}),
        .empty   (o_empty),
-        .full    (dfqq_full)
+        .full    (dfqq_full),
+        `UNUSED_PIN(size)
    );

    assign use_per_bqual_bank_dram_fill_req_valid = use_empty ? (out_per_bank_dram_fill_req_valid & {NUM_BANKS{!o_empty}}) : (use_per_bank_dram_fill_req_valid & {NUM_BANKS{!use_empty}});