rtl refactoring

hw/rtl/cache/VX_bank.v

@@ -150,7 +150,8 @@ module VX_bank #(
         .pop     (snrq_pop),
         .data_out({snrq_addr_st0, snrq_tag_st0}),
         .empty   (snrq_empty),
-        .full    (snrq_full)
+        .full    (snrq_full),
+        `UNUSED_PIN(size)
     );
 
     assign snp_req_ready = ~snrq_full;
@@ -172,7 +173,8 @@ module VX_bank #(
         .pop     (dfpq_pop),
         .data_out({dfpq_addr_st0, dfpq_filldata_st0}),
         .empty   (dfpq_empty),
-        .full    (dfpq_full)
+        .full    (dfpq_full),
+        `UNUSED_PIN(size)
     );
 
     assign dram_fill_rsp_ready = !dfpq_full;
@@ -467,7 +469,7 @@ module VX_bank #(
         .stall(stall_bank_pipe),
         .flush(1'b0),
         .in  ({mrvq_init_ready_state_st1e, snp_to_mrvq_st1e, is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], wsel_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}),
-        .out ({mrvq_init_ready_state_unqual_st2,  snp_to_mrvq_st2 , is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2                   , valid_st2        , addr_st2                  , wsel_st2,                   writeword_st2                  , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2                  })
+        .out ({mrvq_init_ready_state_unqual_st2,  snp_to_mrvq_st2 , is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2                   , valid_st2        , addr_st2                  , wsel_st2,                   writeword_st2                  , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2           })
     );    
 
 
@@ -582,7 +584,8 @@ module VX_bank #(
         .pop     (cwbq_pop),
         .data_out({core_rsp_tid, core_rsp_tag, core_rsp_data}),
         .empty   (cwbq_empty),
-        .full    (cwbq_full)
+        .full    (cwbq_full),
+        `UNUSED_PIN(size)
     );    
 
     assign core_rsp_valid = !cwbq_empty;
@@ -651,7 +654,8 @@ module VX_bank #(
         .pop     (dwbq_pop),
         .data_out({dwbq_is_dwb_out, dwbq_is_snp_out, dram_wb_req_addr, dram_wb_req_data, snp_rsp_tag}),
         .empty   (dwbq_empty),
-        .full    (dwbq_full)
+        .full    (dwbq_full),
+        `UNUSED_PIN(size)
     );       
 
     wire dram_wb_req_fire = dram_wb_req_valid && dram_wb_req_ready;

hw/rtl/cache/VX_cache_dfq_queue.v

@@ -50,7 +50,8 @@ module VX_cache_dfq_queue #(
         .pop     (pop_qual),
         .data_out({out_per_bank_dram_fill_req_valid, out_per_bank_dram_fill_req_addr}),
         .empty   (o_empty),
-        .full    (dfqq_full)
+        .full    (dfqq_full),
+        `UNUSED_PIN(size)
     );
 
     assign use_per_bqual_bank_dram_fill_req_valid = use_empty ? (out_per_bank_dram_fill_req_valid & {NUM_BANKS{!o_empty}}) : (use_per_bank_dram_fill_req_valid & {NUM_BANKS{!use_empty}}); 

hw/rtl/cache/VX_cache_miss_resrv.v

@@ -77,7 +77,7 @@ module VX_cache_miss_resrv #(
     reg [MRVQ_SIZE-1:0] valid_address_match;
 
     genvar i;
-    generate
+    generate         
         for (i = 0; i < MRVQ_SIZE; i++) begin
             assign valid_address_match[i] = valid_table[i] && (addr_table[i] === fill_addr_st1);
             assign make_ready[i]          = is_fill_st1 && valid_address_match[i];
@@ -143,16 +143,17 @@ module VX_cache_miss_resrv #(
         end
     end
 
-`ifdef DBG_PRINT_CACHE_MSRQ
+`ifdef DBG_PRINT_CACHE_MSRQ    
+    integer j;
     always_ff @(posedge clk) begin
         if (mrvq_push || mrvq_pop) begin
             $write("%t: bank%02d:%01d msrq: push=%b pop=%b", $time, CACHE_ID, BANK_ID, mrvq_push, mrvq_pop);
-            for (int i = 0; i < MRVQ_SIZE; i++) begin
-                if (valid_table[i]) begin
+            for (j = 0; j < MRVQ_SIZE; j++) begin
+                if (valid_table[j]) begin
                     $write(" ");                    
-                    if (i == head_ptr) $write("*");
-                    if (~ready_table[i]) $write("!");
-                    $write("addr%0d=%0h", i, `LINE_TO_BYTE_ADDR(addr_table[i], BANK_ID));
+                    if (head_ptr == $bits(head_ptr)'(j)) $write("*");
+                    if (~ready_table[j]) $write("!");
+                    $write("addr%0d=%0h", j, `LINE_TO_BYTE_ADDR(addr_table[j], BANK_ID));
                 end
             end
             $write("\n");

hw/rtl/cache/VX_cache_req_queue.v

@@ -83,7 +83,8 @@ module VX_cache_req_queue #(
         .pop      (pop_qual),
         .data_out ({out_per_valids, out_per_addr, out_per_writedata, out_per_tag, out_per_mem_read, out_per_mem_write}),
         .empty    (o_empty),
-        .full     (reqq_full)
+        .full     (reqq_full),
+        `UNUSED_PIN(size)
     );
 
     wire[NUM_REQUESTS-1:0] real_out_per_valids = out_per_valids & {NUM_REQUESTS{~out_empty}};

hw/rtl/cache/VX_prefetcher.v

@@ -46,7 +46,8 @@ module VX_prefetcher #(
         .data_out(current_addr),
 
         .empty   (current_empty),
-        .full    (current_full)
+        .full    (current_full),
+        `UNUSED_PIN(size)
     );
 
     assign pref_valid = 0; // TODO use_valid != 0;