rtl refactoring

2020-05-20 16:59:14 -04:00
parent b5569dd525
commit cefd0d85af
11 changed files with 59 additions and 55 deletions
--- a/hw/rtl/VX_lsu_addr_gen.v
+++ b/hw/rtl/VX_lsu_addr_gen.v
@@ -3,8 +3,7 @@
 module VX_lsu_addr_gen (
    input  wire[`NUM_THREADS-1:0][31:0] base_address,
    input  wire[31:0]                   offset,
-    output wire[`NUM_THREADS-1:0][31:0] address
-    
+    output wire[`NUM_THREADS-1:0][31:0] address    
 );
    genvar i;
    generate