minor updates
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@@ -21,7 +21,7 @@ module VX_pending_size #(
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset) begin
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if (reset) begin
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used_r <= 0;
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used_r <= 0;
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empty_r <= 0;
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empty_r <= 1;
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full_r <= 0;
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full_r <= 0;
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end else begin
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end else begin
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assert(!push || !full);
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assert(!push || !full);
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