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minor updates

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This commit is contained in:
Blaise Tine
2021-01-18 04:22:40 -08:00
parent 9bce15a513
commit ce9ef840d6
12 changed files with 1714 additions and 3297 deletions
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2
benchmarks/riscv_tests/isa/Makefile
View File

@@ -3,4 +3,4 @@ VTESTS := $(wildcard *-v-*.hex)
TESTS := $(filter-out $(VTESTS) rv32si-p-scall.hex rv32si-p-sbreak.hex rv32mi-p-breakpoint.hex rv32ud-p-fclass.hex rv32ua-p-amomax_w.hex rv32ua-p-amoxor_w.hex rv32ud-p-ldst.hex rv32ua-p-amoor_w.hex rv32mi-p-ma_addr.hex rv32ud-p-fdiv.hex rv32ud-p-fcmp.hex rv32mi-p-mcsr.hex rv32ua-p-amoswap_w.hex rv32mi-p-ma_fetch.hex rv32mi-p-csr.hex rv32ua-p-amoadd_w.hex rv32si-p-dirty.hex rv32ud-p-fcvt.hex rv32ui-p-fence_i.hex rv32si-p-csr.hex rv32mi-p-shamt.hex rv32ua-p-amomin_w.hex rv32ua-p-lrsc.hex rv32ud-p-fmadd.hex rv32ud-p-fadd.hex rv32si-p-wfi.hex rv32ua-p-amomaxu_w.hex rv32si-p-ma_fetch.hex rv32ud-p-fmin.hex rv32mi-p-illegal.hex rv32uc-p-rvc.hex rv32mi-p-sbreak.hex rv32ua-p-amominu_w.hex rv32ua-p-amoand_w.hex, $(TESTS)) TESTS := $(filter-out $(VTESTS) rv32si-p-scall.hex rv32si-p-sbreak.hex rv32mi-p-breakpoint.hex rv32ud-p-fclass.hex rv32ua-p-amomax_w.hex rv32ua-p-amoxor_w.hex rv32ud-p-ldst.hex rv32ua-p-amoor_w.hex rv32mi-p-ma_addr.hex rv32ud-p-fdiv.hex rv32ud-p-fcmp.hex rv32mi-p-mcsr.hex rv32ua-p-amoswap_w.hex rv32mi-p-ma_fetch.hex rv32mi-p-csr.hex rv32ua-p-amoadd_w.hex rv32si-p-dirty.hex rv32ud-p-fcvt.hex rv32ui-p-fence_i.hex rv32si-p-csr.hex rv32mi-p-shamt.hex rv32ua-p-amomin_w.hex rv32ua-p-lrsc.hex rv32ud-p-fmadd.hex rv32ud-p-fadd.hex rv32si-p-wfi.hex rv32ua-p-amomaxu_w.hex rv32si-p-ma_fetch.hex rv32ud-p-fmin.hex rv32mi-p-illegal.hex rv32uc-p-rvc.hex rv32mi-p-sbreak.hex rv32ua-p-amominu_w.hex rv32ua-p-amoand_w.hex, $(TESTS))
run: run:
cd ../../../hw/simulate/obj_dir && ./VVortex -f $(foreach test,$(TESTS),../../../benchmarks/riscv_tests/isa/$(test)) cd ../../../hw/simulate/obj_dir && ./VVortex -r $(foreach test,$(TESTS),../../../benchmarks/riscv_tests/isa/$(test))

12
hw/rtl/VX_config.vh
View File

@@ -108,7 +108,7 @@
`ifdef ALTERA_S10 `ifdef ALTERA_S10
`define LATENCY_FDIV 34 `define LATENCY_FDIV 34
`else `else
`define LATENCY_FDIV 20 `define LATENCY_FDIV 15
`endif `endif
`endif `endif
@@ -116,18 +116,10 @@
`ifdef ALTERA_S10 `ifdef ALTERA_S10
`define LATENCY_FSQRT 25 `define LATENCY_FSQRT 25
`else `else
`define LATENCY_FSQRT 15 `define LATENCY_FSQRT 10
`endif `endif
`endif `endif
`ifndef LATENCY_ITOF
`define LATENCY_ITOF 7
`endif
`ifndef LATENCY_FTOI
`define LATENCY_FTOI 3
`endif
`ifndef LATENCY_FDIVSQRT `ifndef LATENCY_FDIVSQRT
`define LATENCY_FDIVSQRT 32 `define LATENCY_FDIVSQRT 32
`endif `endif

2850
hw/rtl/fp_cores/altera/arria10/acl_fdiv.sv
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File diff suppressed because it is too large Load Diff

2
hw/rtl/fp_cores/altera/arria10/acl_fmadd.sv
View File

@@ -16,7 +16,7 @@
// --------------------------------------------------------------------------- // ---------------------------------------------------------------------------
// SystemVerilog created from acl_fmadd // SystemVerilog created from acl_fmadd
// SystemVerilog created on Sun Dec 27 09:47:20 2020 // SystemVerilog created on Mon Jan 18 04:15:46 2021
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)

1593
hw/rtl/fp_cores/altera/arria10/acl_fsqrt.sv
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File diff suppressed because it is too large Load Diff

246
hw/rtl/fp_cores/altera/arria10/acl_gen.log
View File

@@ -4,97 +4,7 @@ argc=22
Generation context: Generation context:
Will not generate valid and channel signals Will not generate valid and channel signals
HardFP is enabled enabling set to true HardFP is enabled enabling set to true
Correct rounding constraint detected Faithful rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_fadd
Frequency 250MHz
Deployment FPGA Arria10
Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0
The pipeline depth of the block is 3 cycle(s)
@@start
@name FPAdd@
@latency 3@
@LUT 0@
@DSP 2@
@RAMBits 0@
@RAMBlockUsage 0@
@enable 1@
@subnormals 0@
@error 0.50@
@rounding RNE@
@method single path@
@inPort 0 fpieee 8 23@
@inPort 1 fpieee 8 23@
@outPort 0 fpieee 8 23@
@nochanvalid 1@
@@end
starting execution ...
build model options ...
argc=22
Generation context:
Will not generate valid and channel signals
HardFP is enabled enabling set to true
Correct rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_fsub
Frequency 250MHz
Deployment FPGA Arria10
Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0
The pipeline depth of the block is 3 cycle(s)
@@start
@name FPSub@
@latency 3@
@LUT 0@
@DSP 2@
@RAMBits 0@
@RAMBlockUsage 0@
@enable 1@
@subnormals 0@
@error 0.50@
@rounding RNE@
@method single path@
@inPort 0 fpieee 8 23@
@inPort 1 fpieee 8 23@
@outPort 0 fpieee 8 23@
@nochanvalid 1@
@@end
starting execution ...
build model options ...
argc=22
Generation context:
Will not generate valid and channel signals
HardFP is enabled enabling set to true
Correct rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_fmul
Frequency 250MHz
Deployment FPGA Arria10
Estimated resources LUTs 0, DSPs 2, RAMBits 0, RAMBlocks 0
The pipeline depth of the block is 3 cycle(s)
@@start
@name FPMul@
@latency 3@
@LUT 0@
@DSP 2@
@RAMBits 0@
@RAMBlockUsage 0@
@enable 1@
@subnormals 0@
@error 0.50@
@rounding RNE@
@method default@
@inPort 0 fpieee 8 23@
@inPort 1 fpieee 8 23@
@outPort 0 fpieee 8 23@
@nochanvalid 1@
@@end
starting execution ...
build model options ...
argc=22
Generation context:
Will not generate valid and channel signals
HardFP is enabled enabling set to true
Correct rounding constraint detected
Will not generate valid and channel signals Will not generate valid and channel signals
The new component name is acl_fmadd The new component name is acl_fmadd
Frequency 250MHz Frequency 250MHz
@@ -110,8 +20,8 @@ The pipeline depth of the block is 4 cycle(s)
@RAMBlockUsage 0@ @RAMBlockUsage 0@
@enable 1@ @enable 1@
@subnormals 0@ @subnormals 0@
@error 0.50@ @error 1.00@
@rounding RNE@ @rounding NA@
@method multadd@ @method multadd@
@inPort 0 fpieee 8 23@ @inPort 0 fpieee 8 23@
@inPort 1 fpieee 8 23@ @inPort 1 fpieee 8 23@
@@ -125,24 +35,24 @@ argc=23
Generation context: Generation context:
Will not generate valid and channel signals Will not generate valid and channel signals
HardFP is enabled enabling set to true HardFP is enabled enabling set to true
Correct rounding constraint detected Faithful rounding constraint detected
Will not generate valid and channel signals Will not generate valid and channel signals
The new component name is acl_fdiv The new component name is acl_fdiv
Frequency 250MHz Frequency 250MHz
Deployment FPGA Arria10 Deployment FPGA Arria10
Estimated resources LUTs 1067, DSPs 7, RAMBits 34304, RAMBlocks 3 Estimated resources LUTs 539, DSPs 5, RAMBits 32768, RAMBlocks 3
The pipeline depth of the block is 20 cycle(s) The pipeline depth of the block is 15 cycle(s)
@@start @@start
@name FPDiv@ @name FPDiv@
@latency 20@ @latency 15@
@LUT 1067@ @LUT 539@
@DSP 7@ @DSP 5@
@RAMBits 34304@ @RAMBits 32768@
@RAMBlockUsage 3@ @RAMBlockUsage 3@
@enable 1@ @enable 1@
@subnormals 0@ @subnormals 0@
@error 0.50@ @error 1.00@
@rounding RNE@ @rounding NA@
@method polynomial approximation@ @method polynomial approximation@
@inPort 0 fpieee 8 23@ @inPort 0 fpieee 8 23@
@inPort 1 fpieee 8 23@ @inPort 1 fpieee 8 23@
@@ -155,142 +65,26 @@ argc=22
Generation context: Generation context:
Will not generate valid and channel signals Will not generate valid and channel signals
HardFP is enabled enabling set to true HardFP is enabled enabling set to true
Correct rounding constraint detected Faithful rounding constraint detected
Will not generate valid and channel signals Will not generate valid and channel signals
The new component name is acl_fsqrt The new component name is acl_fsqrt
Frequency 250MHz Frequency 250MHz
Deployment FPGA Arria10 Deployment FPGA Arria10
Estimated resources LUTs 518, DSPs 5, RAMBits 15872, RAMBlocks 3 Estimated resources LUTs 271, DSPs 3, RAMBits 15872, RAMBlocks 3
The pipeline depth of the block is 15 cycle(s) The pipeline depth of the block is 10 cycle(s)
@@start @@start
@name FPSqrt@ @name FPSqrt@
@latency 15@ @latency 10@
@LUT 518@ @LUT 271@
@DSP 5@ @DSP 3@
@RAMBits 15872@ @RAMBits 15872@
@RAMBlockUsage 3@ @RAMBlockUsage 3@
@enable 1@ @enable 1@
@subnormals 0@ @subnormals 0@
@error 0.50@ @error 1.00@
@rounding RNE@ @rounding NA@
@method polynomial approximation@ @method polynomial approximation@
@inPort 0 fpieee 8 23@ @inPort 0 fpieee 8 23@
@outPort 0 fpieee 8 23@ @outPort 0 fpieee 8 23@
@nochanvalid 1@ @nochanvalid 1@
@@end @@end
starting execution ...
build model options ...
argc=25
Generation context:
Will not generate valid and channel signals
HardFP is enabled enabling set to true
Correct rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_ftoi
Frequency 250MHz
Deployment FPGA Arria10
Estimated resources LUTs 327, DSPs 0, RAMBits 0, RAMBlocks 0
The pipeline depth of the block is 3 cycle(s)
@@start
@name FPToFXP@
@latency 3@
@LUT 327@
@DSP 0@
@RAMBits 0@
@RAMBlockUsage 0@
@enable 1@
@subnormals 0@
@error 0.50@
@rounding RNE@
@method default@
@inPort 0 fpieee 8 23@
@outPort 0 fxp 32 0 1@
@nochanvalid 1@
@@end
starting execution ...
build model options ...
argc=25
Generation context:
Will not generate valid and channel signals
HardFP is enabled enabling set to true
Correct rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_ftou
Frequency 250MHz
Deployment FPGA Arria10
Estimated resources LUTs 287, DSPs 0, RAMBits 0, RAMBlocks 0
The pipeline depth of the block is 3 cycle(s)
@@start
@name FPToFXP@
@latency 3@
@LUT 287@
@DSP 0@
@RAMBits 0@
@RAMBlockUsage 0@
@enable 1@
@subnormals 0@
@error 0.50@
@rounding RNE@
@method default@
@inPort 0 fpieee 8 23@
@outPort 0 fxp 32 0 0@
@nochanvalid 1@
@@end
starting execution ...
build model options ...
argc=25
Generation context:
Will not generate valid and channel signals
HardFP is enabled enabling set to true
Correct rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_itof
Frequency 250MHz
Deployment FPGA Arria10
Estimated resources LUTs 397, DSPs 0, RAMBits 0, RAMBlocks 0
The pipeline depth of the block is 7 cycle(s)
@@start
@name FXPToFP@
@latency 7@
@LUT 397@
@DSP 0@
@RAMBits 0@
@RAMBlockUsage 0@
@enable 1@
@subnormals 0@
@error 0.50@
@rounding RNE@
@method default@
@inPort 0 fxp 32 0 1@
@outPort 0 fpieee 8 23@
@nochanvalid 1@
@@end
starting execution ...
build model options ...
argc=25
Generation context:
Will not generate valid and channel signals
HardFP is enabled enabling set to true
Correct rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_utof
Frequency 300MHz
Deployment FPGA Arria10
Estimated resources LUTs 363, DSPs 0, RAMBits 0, RAMBlocks 0
The pipeline depth of the block is 7 cycle(s)
@@start
@name FXPToFP@
@latency 7@
@LUT 363@
@DSP 0@
@RAMBits 0@
@RAMBlockUsage 0@
@enable 1@
@subnormals 0@
@error 0.50@
@rounding RNE@
@method default@
@inPort 0 fxp 32 0 0@
@outPort 0 fpieee 8 23@
@nochanvalid 1@
@@end

2
hw/rtl/fp_cores/altera/arria10/acl_gen.sh
View File

@@ -5,7 +5,7 @@ PREFIX=acl
CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64 CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64
OPTIONS="-target $FAMILY -noChanValid -enable -enableHardFP 1 -printMachineReadable -lang verilog -correctRounding -noChanValid -enable -speedgrade 2" OPTIONS="-target $FAMILY -noChanValid -enable -enableHardFP 1 -printMachineReadable -lang verilog -faithfulRounding -noChanValid -enable -speedgrade 2"
export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH

298
hw/simulate/testbench.cpp
View File

@@ -5,153 +5,187 @@
//#define ALL_TESTS //#define ALL_TESTS
static void show_usage() {
std::cout << "Usage: [-r] [-h: help] programs.." << std::endl;
}
bool riscv_test = false;
std::vector<const char*> programs;
static void parse_args(int argc, char **argv) {
int c;
while ((c = getopt(argc, argv, "rh?")) != -1) {
switch (c) {
case 'r':
riscv_test = true;
break;
case 'h':
case '?':
show_usage();
exit(0);
break;
default:
show_usage();
exit(-1);
}
}
for (int i = optind; i < argc; ++i) {
programs.push_back(argv[i]);
}
}
int main(int argc, char **argv) { int main(int argc, char **argv) {
bool passed = true; bool passed = true;
if (argc == 1) { if (argc == 1) {
#ifdef ALL_TESTS #ifdef ALL_TESTS
std::string tests[] = { std::string tests[] = {
"../../../benchmarks/riscv_tests/isa/rv32ui-p-add.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-add.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-addi.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-addi.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-and.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-and.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-andi.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-andi.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-auipc.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-auipc.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-beq.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-beq.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-bge.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-bge.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-bgeu.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-bgeu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-blt.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-blt.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-bltu.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-bltu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-bne.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-bne.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-jal.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-jal.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-jalr.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-jalr.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lb.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-lb.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lbu.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-lbu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lh.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-lh.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lhu.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-lhu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lui.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-lui.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-lw.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-lw.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-or.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-or.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-ori.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-ori.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sb.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-sb.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sh.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-sh.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-simple.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-simple.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sll.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-sll.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-slli.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-slli.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-slt.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-slt.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-slti.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-slti.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sltiu.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-sltiu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sltu.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-sltu.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sra.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-sra.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-srai.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-srai.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-srl.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-srl.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-srli.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-srli.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sub.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-sub.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-sw.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-sw.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-xor.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-xor.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-xori.hex", "../../../benchmarks/riscv_tests/isa/rv32ui-p-xori.hex",
#ifdef EXT_M_ENABLE #ifdef EXT_M_ENABLE
"../../../benchmarks/riscv_tests/isa/rv32um-p-div.hex", "../../../benchmarks/riscv_tests/isa/rv32um-p-div.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-divu.hex", "../../../benchmarks/riscv_tests/isa/rv32um-p-divu.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-mul.hex", "../../../benchmarks/riscv_tests/isa/rv32um-p-mul.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-mulh.hex", "../../../benchmarks/riscv_tests/isa/rv32um-p-mulh.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-mulhsu.hex", "../../../benchmarks/riscv_tests/isa/rv32um-p-mulhsu.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-mulhu.hex", "../../../benchmarks/riscv_tests/isa/rv32um-p-mulhu.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-rem.hex", "../../../benchmarks/riscv_tests/isa/rv32um-p-rem.hex",
"../../../benchmarks/riscv_tests/isa/rv32um-p-remu.hex", "../../../benchmarks/riscv_tests/isa/rv32um-p-remu.hex",
#endif #endif
}; };
std::string tests_fp[] = { std::string tests_fp[] = {
#ifdef EXT_F_ENABLE #ifdef EXT_F_ENABLE
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fadd.hex", "../../../benchmarks/riscv_tests/isa/rv32uf-p-fadd.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fdiv.hex", "../../../benchmarks/riscv_tests/isa/rv32uf-p-fmadd.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fmadd.hex", "../../../benchmarks/riscv_tests/isa/rv32uf-p-fmin.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fmin.hex", "../../../benchmarks/riscv_tests/isa/rv32uf-p-fcmp.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fcmp.hex", "../../../benchmarks/riscv_tests/isa/rv32uf-p-ldst.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-ldst.hex", "../../../benchmarks/riscv_tests/isa/rv32uf-p-fcvt.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fcvt.hex", "../../../benchmarks/riscv_tests/isa/rv32uf-p-fcvt_w.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fcvt_w.hex", "../../../benchmarks/riscv_tests/isa/rv32uf-p-move.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-fclass.hex", "../../../benchmarks/riscv_tests/isa/rv32uf-p-recoding.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-move.hex", "../../../benchmarks/riscv_tests/isa/rv32uf-p-fdiv.hex",
"../../../benchmarks/riscv_tests/isa/rv32uf-p-recoding.hex", "../../../benchmarks/riscv_tests/isa/rv32uf-p-fclass.hex",
#endif #endif
}; };
for (std::string test : tests) { for (std::string test : tests) {
std::cout << "\n---------------------------------------\n"; std::cout << "\n---------------------------------------\n";
std::cout << test << std::endl;
RAM ram;
Simulator simulator;
simulator.attach_ram(&ram);
simulator.load_ihex(test.c_str());
simulator.run();
bool status = (1 == simulator.get_last_wb_value(3));
if (status) std::cout << "Passed: " << test << std::endl;
if (!status) std::cout << "Failed: " << test << std::endl;
passed = passed && status;
if (!passed)
break;
}
for (std::string test : tests_fp) {
std::cout << "\n---------------------------------------\n";
std::cout << test << std::endl;
RAM ram;
Simulator simulator;
simulator.attach_ram(&ram);
simulator.load_ihex(test.c_str());
simulator.run();
bool status = (1 == simulator.get_last_wb_value(3));
if (status) std::cout << "Passed: " << test << std::endl;
if (!status) std::cout << "Failed: " << test << std::endl;
passed = passed && status;
if (!passed)
break;
}
std::cout << "\n***************************************\n";
if (passed) std::cout << "PASSED ALL TESTS\n";
if (!passed) std::cout << "Failed one or more tests\n";
#else
char test[] = "../../../runtime/tests/simple/vx_simple.hex";
std::cout << test << std::endl; std::cout << test << std::endl;
RAM ram; RAM ram;
Simulator simulator; Simulator simulator;
simulator.attach_ram(&ram); simulator.attach_ram(&ram);
simulator.load_ihex(test.c_str()); simulator.load_ihex(test);
simulator.run(); simulator.run();
bool status = (1 == simulator.get_last_wb_value(3)); #endif
if (status) std::cout << "Passed: " << test << std::endl; } else {
if (!status) std::cout << "Failed: " << test << std::endl; parse_args(argc, argv);
passed = passed && status;
if (!passed) for (auto program : programs) {
break; std::cout << "Running " << program << " .." << std::endl;
RAM ram;
Simulator simulator;
simulator.attach_ram(&ram);
simulator.load_ihex(program);
simulator.run();
if (riscv_test) {
bool status = (1 == simulator.get_last_wb_value(3));
if (status) std::cout << "Passed." << std::endl;
if (!status) std::cout << "Failed." << std::endl;
passed = passed && status;
if (!passed)
break;
}
}
} }
for (std::string test : tests_fp) {
std::cout << "\n---------------------------------------\n";
std::cout << test << std::endl;
RAM ram;
Simulator simulator;
simulator.attach_ram(&ram);
simulator.load_ihex(test.c_str());
simulator.run();
bool status = (1 == simulator.get_last_wb_value(3));
if (status) std::cout << "Passed: " << test << std::endl;
if (!status) std::cout << "Failed: " << test << std::endl;
passed = passed && status;
if (!passed)
break;
}
std::cout << "\n***************************************\n";
if (passed) std::cout << "PASSED ALL TESTS\n";
if (!passed) std::cout << "Failed one or more tests\n";
return !passed; return !passed;
#else
char test[] = "../../../runtime/tests/simple/vx_simple.hex";
std::cout << test << std::endl;
RAM ram;
Simulator simulator;
simulator.attach_ram(&ram);
simulator.load_ihex(test);
simulator.run();
return 0;
#endif
} else {
std::vector<std::string> tests(argv+2, argv+argc);
for (std::string test : tests) {
std::cout << test << std::endl;
RAM ram;
Simulator simulator;
simulator.attach_ram(&ram);
simulator.load_ihex(test.c_str());
simulator.run();
}
return 0;
}
} }

2
runtime/tests/dev/Makefile
View File

@@ -28,7 +28,7 @@ $(PROJECT).elf: $(SRCS)
$(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf $(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf
run: $(PROJECT).hex run: $(PROJECT).hex
(cd ../../../hw/simulate/obj_dir && ./VVortex -f ../../../runtime/tests/dev/$(PROJECT).hex) (cd ../../../hw/simulate/obj_dir && ./VVortex ../../../runtime/tests/dev/$(PROJECT).hex)
.depend: $(SRCS) .depend: $(SRCS)
$(CC) $(CFLAGS) -MM $^ > .depend; $(CC) $(CFLAGS) -MM $^ > .depend;

2
runtime/tests/hello/Makefile
View File

@@ -28,7 +28,7 @@ $(PROJECT).elf: $(SRCS)
$(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf $(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf
run: $(PROJECT).hex run: $(PROJECT).hex
(cd ../../../hw/simulate/obj_dir && ./VVortex -f ../../../runtime/tests/hello/$(PROJECT).hex) (cd ../../../hw/simulate/obj_dir && ./VVortex ../../../runtime/tests/hello/$(PROJECT).hex)
.depend: $(SRCS) .depend: $(SRCS)
$(CC) $(CFLAGS) -MM $^ > .depend; $(CC) $(CFLAGS) -MM $^ > .depend;

2
runtime/tests/nlTest/Makefile
View File

@@ -28,7 +28,7 @@ $(PROJECT).elf: $(SRCS)
$(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf $(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf
run: $(PROJECT).hex run: $(PROJECT).hex
(cd ../../../hw/simulate/obj_dir && ./VVortex -f ../../../runtime/tests/nlTest/$(PROJECT).hex) (cd ../../../hw/simulate/obj_dir && ./VVortex ../../../runtime/tests/nlTest/$(PROJECT).hex)
.depend: $(SRCS) .depend: $(SRCS)
$(CC) $(CFLAGS) -MM $^ > .depend; $(CC) $(CFLAGS) -MM $^ > .depend;

2
runtime/tests/simple/Makefile
View File

@@ -28,7 +28,7 @@ $(PROJECT).elf: $(SRCS)
$(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf $(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf
run: $(PROJECT).hex run: $(PROJECT).hex
(cd ../../../hw/simulate/obj_dir && ./VVortex -f ../../../runtime/tests/simple/$(PROJECT).hex) (cd ../../../hw/simulate/obj_dir && ./VVortex ../../../runtime/tests/simple/$(PROJECT).hex)
.depend: $(SRCS) .depend: $(SRCS)
$(CC) $(CFLAGS) -MM $^ > .depend; $(CC) $(CFLAGS) -MM $^ > .depend;