add tag to tc smem interface
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@@ -6,7 +6,8 @@ module Vortex import VX_gpu_pkg::*; #(
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parameter CORE_ID = 0,
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parameter TENSOR_FP16 = 0,
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parameter BOOTROM_HANG100 = 32'h10100,
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parameter NUM_THREADS = 0
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parameter NUM_THREADS = 0,
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parameter TC_TAG_WIDTH = 4
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) (
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/* adapt to CoreIO bundle at src/main/scala/tile/Core.scala */
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@@ -78,9 +79,11 @@ module Vortex import VX_gpu_pkg::*; #(
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input [1:0] tc_a_ready,
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output [1:0] tc_a_valid,
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output [63:0] tc_a_bits_address,
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input [511:0] tc_d_bits_data,
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output [2 * TC_TAG_WIDTH - 1:0] tc_a_bits_tag,
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output [1:0] tc_d_ready,
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input [1:0] tc_d_valid,
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input [511:0] tc_d_bits_data,
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input [2 * TC_TAG_WIDTH - 1:0] tc_d_bits_tag,
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// gbar ------------------------------------------------
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@@ -298,16 +301,19 @@ module Vortex import VX_gpu_pkg::*; #(
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endgenerate
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// tc ---------------------------------------------------------------------
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VX_tc_bus_if tc_p0_bus_if();
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VX_tc_bus_if tc_p1_bus_if();
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VX_tc_bus_if #(.TAG_WIDTH(TC_TAG_WIDTH)) tc_p0_bus_if();
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VX_tc_bus_if #(.TAG_WIDTH(TC_TAG_WIDTH)) tc_p1_bus_if();
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assign tc_a_valid = {tc_p1_bus_if.req_valid, tc_p0_bus_if.req_valid};
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assign tc_a_bits_address = {tc_p1_bus_if.req_data, tc_p0_bus_if.req_data};
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assign tc_a_bits_address = {tc_p1_bus_if.req_data.addr, tc_p0_bus_if.req_data.addr};
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assign tc_a_bits_tag = {tc_p1_bus_if.req_data.tag, tc_p0_bus_if.req_data.tag};
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assign tc_p0_bus_if.req_ready = tc_a_ready[0];
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assign tc_p0_bus_if.rsp_valid = tc_d_valid[0];
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assign tc_p0_bus_if.rsp_data = tc_d_bits_data[0];
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assign tc_p0_bus_if.rsp_data.data = tc_d_bits_data[0];
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assign tc_p0_bus_if.rsp_data.tag = tc_d_bits_tag[0];
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assign tc_p1_bus_if.req_ready = tc_a_ready[1];
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assign tc_p1_bus_if.rsp_valid = tc_d_valid[1];
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assign tc_p1_bus_if.rsp_data = tc_d_bits_data[1];
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assign tc_p1_bus_if.rsp_data.data = tc_d_bits_data[1];
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assign tc_p1_bus_if.rsp_data.tag = tc_d_bits_tag[1];
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assign tc_d_ready = {tc_p1_bus_if.rsp_ready, tc_p0_bus_if.rsp_ready};
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// gbar -------------------------------------------------------------------
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