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minor improvement

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This commit is contained in:
Blaise Tine
2020-11-03 17:08:26 -08:00
parent 323d2a3b3e
commit cd8ce20bd6
2 changed files with 5 additions and 5 deletions
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4
hw/rtl/cache/VX_cache_miss_resrv.v vendored
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@@ -56,7 +56,7 @@ module VX_cache_miss_resrv #(
// fill
input wire update_ready_st0,
input wire[`LINE_ADDR_WIDTH-1:0] fill_addr_st0,
input wire[`LINE_ADDR_WIDTH-1:0] addr_st0,
output wire pending_hazard_st0,
// dequeue
@@ -93,7 +93,7 @@ module VX_cache_miss_resrv #(
wire [MRVQ_SIZE-1:0] valid_address_match;
for (genvar i = 0; i < MRVQ_SIZE; i++) begin
assign valid_address_match[i] = valid_table[i] && (addr_table[i] == fill_addr_st0);
assign valid_address_match[i] = valid_table[i] && (addr_table[i] == addr_st0);
end
assign pending_hazard_st0 = (| valid_address_match);