From cd8ce20bd6911c6047ecffa5174b12d280203b1a Mon Sep 17 00:00:00 2001
From: Blaise Tine <tinebp@iam-ssh1.research.intel-research.net>
Date: Tue, 3 Nov 2020 17:08:26 -0800
Subject: [PATCH] minor improvement

---
 hw/rtl/cache/VX_bank.v             | 6 +++---
 hw/rtl/cache/VX_cache_miss_resrv.v | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v
index a0746f36..7dbb6efc 100644
--- a/hw/rtl/cache/VX_bank.v
+++ b/hw/rtl/cache/VX_bank.v
@@ -339,7 +339,7 @@ module VX_bank #(
                                 reqq_pop_unqual ? reqq_req_writeword_st0 :
                                     0;
 
-    // we have a miss in msrq or going into it for the current address
+    // we have a miss in msrq or in stage 2 for the current address
     wire msrq_pending_hazard_st0 = msrq_pending_hazard_unqual_st0 
                                 || (miss_add_unqual && (addr_st2 == addr_st0));
 
@@ -486,7 +486,7 @@ module VX_bank #(
     assign is_msrq_miss_st2 = miss_add_unqual && is_msrq_st2;
 
     // a matching incoming fill request to the block is in stage 0    
-    wire incoming_st0_fill_st2 = is_fill_st0 && (addr_st2 == addr_st0);
+    wire incoming_st0_fill_st2 = is_fill_st0 && (addr_st2 == dfpq_addr_st0);
 
     // a matching incoming fill request to the block is in stage 1
     wire incoming_st1_fill_st2 = is_fill_st1 && (addr_st2 == addr_st1);
@@ -554,7 +554,7 @@ module VX_bank #(
 
             // fill
             .update_ready_st0        (update_ready_st0),
-            .fill_addr_st0           (addr_st0),
+            .addr_st0                (addr_st0),
             .pending_hazard_st0      (msrq_pending_hazard_unqual_st0),
             
             // dequeue
diff --git a/hw/rtl/cache/VX_cache_miss_resrv.v b/hw/rtl/cache/VX_cache_miss_resrv.v
index dbf6759f..4915d29f 100644
--- a/hw/rtl/cache/VX_cache_miss_resrv.v
+++ b/hw/rtl/cache/VX_cache_miss_resrv.v
@@ -56,7 +56,7 @@ module VX_cache_miss_resrv #(
 
     // fill
     input wire                          update_ready_st0,    
-    input wire[`LINE_ADDR_WIDTH-1:0]    fill_addr_st0,
+    input wire[`LINE_ADDR_WIDTH-1:0]    addr_st0,
     output wire                         pending_hazard_st0,
 
     // dequeue
@@ -93,7 +93,7 @@ module VX_cache_miss_resrv #(
 
     wire [MRVQ_SIZE-1:0] valid_address_match;
     for (genvar i = 0; i < MRVQ_SIZE; i++) begin
-        assign valid_address_match[i] = valid_table[i] && (addr_table[i] == fill_addr_st0);
+        assign valid_address_match[i] = valid_table[i] && (addr_table[i] == addr_st0);
     end
 
     assign pending_hazard_st0 = (| valid_address_match);