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multicore fix

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This commit is contained in:
Blaise Tine
2020-05-10 08:30:04 -04:00
parent 359601cfd3
commit cc84e0691c
40 changed files with 27930 additions and 28148 deletions
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47
hw/rtl/cache/VX_cache_dram_req_arb.v vendored
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@@ -1,46 +1,17 @@
`include "VX_cache_config.vh"
module VX_cache_dram_req_arb #(
// Size of cache in bytes
parameter CACHE_SIZE = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE = 16,
parameter BANK_LINE_SIZE = 0,
// Number of banks {1, 2, 4, 8,...}
parameter NUM_BANKS = 8,
parameter NUM_BANKS = 0,
// Size of a word in bytes
parameter WORD_SIZE = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUM_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
parameter STAGE_1_CYCLES = 2,
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
parameter REQQ_SIZE = 8,
// Miss Reserv Queue Knob
parameter MRVQ_SIZE = 8,
// Dram Fill Rsp Queue Size
parameter DFPQ_SIZE = 2,
// Snoop Req Queue
parameter SNRQ_SIZE = 8,
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
parameter CWBQ_SIZE = 8,
// Dram Writeback Queue Size
parameter DWBQ_SIZE = 4,
parameter WORD_SIZE = 0,
// Dram Fill Req Queue Size
parameter DFQQ_SIZE = 8,
// Lower Level Cache Hit Queue Size
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Prefetcher
parameter PRFQ_SIZE = 64,
parameter PRFQ_STRIDE = 2
parameter DFQQ_SIZE = 0,
// Prefetcher
parameter PRFQ_SIZE = 0,
parameter PRFQ_STRIDE = 0
) (
input wire clk,
input wire reset,
@@ -101,7 +72,9 @@ module VX_cache_dram_req_arb #(
wire dfqq_push = (| per_bank_dram_fill_req_valid);
VX_cache_dfq_queue #(
.BANK_LINE_SIZE(BANK_LINE_SIZE),
.NUM_BANKS(NUM_BANKS),
.DFQQ_SIZE(DFQQ_SIZE)
) cache_dfq_queue (
.clk (clk),
.reset (reset),