multicore fix
This commit is contained in:
82
hw/rtl/cache/VX_bank.v
vendored
82
hw/rtl/cache/VX_bank.v
vendored
@@ -2,54 +2,54 @@
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`include "VX_define.vh"
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module VX_bank #(
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// Size of cache in bytes
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parameter CACHE_SIZE = 1024,
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parameter CACHE_SIZE = 0,
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE = 16,
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parameter BANK_LINE_SIZE = 0,
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// Number of banks {1, 2, 4, 8,...}
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parameter NUM_BANKS = 8,
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parameter NUM_BANKS = 0,
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// Size of a word in bytes
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parameter WORD_SIZE = 4,
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parameter WORD_SIZE = 0,
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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parameter NUM_REQUESTS = 2,
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parameter NUM_REQUESTS = 0,
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// Number of cycles to complete i 1 (read from memory)
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parameter STAGE_1_CYCLES = 2,
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parameter STAGE_1_CYCLES = 0,
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Core Request Queue Size
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parameter REQQ_SIZE = 8,
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parameter REQQ_SIZE = 0,
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// Miss Reserv Queue Knob
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parameter MRVQ_SIZE = 8,
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parameter MRVQ_SIZE = 0,
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// Dram Fill Rsp Queue Size
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parameter DFPQ_SIZE = 2,
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parameter DFPQ_SIZE = 0,
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// Snoop Req Queue
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parameter SNRQ_SIZE = 8,
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parameter SNRQ_SIZE = 0,
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Core Writeback Queue Size
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parameter CWBQ_SIZE = 8,
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parameter CWBQ_SIZE = 0,
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// Dram Writeback Queue Size
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parameter DWBQ_SIZE = 4,
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parameter DWBQ_SIZE = 0,
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// Dram Fill Req Queue Size
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parameter DFQQ_SIZE = 8,
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parameter DFQQ_SIZE = 0,
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// Lower Level Cache Hit Queue Size
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parameter LLVQ_SIZE = 16,
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parameter LLVQ_SIZE = 0,
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// Fill Forward SNP Queue
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parameter FFSQ_SIZE = 8,
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parameter FFSQ_SIZE = 0,
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// Fill Invalidator Size {Fill invalidator must be active}
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parameter FILL_INVALIDAOR_SIZE = 16,
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parameter FILL_INVALIDAOR_SIZE = 0,
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// Enable cache writeable
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parameter WRITE_ENABLE = 1,
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parameter WRITE_ENABLE = 0,
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// Enable dram update
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parameter DRAM_ENABLE = 1,
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parameter DRAM_ENABLE = 0,
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// Enable snoop forwarding
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parameter SNOOP_FORWARDING = 0,
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// core request tag size
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parameter CORE_TAG_WIDTH = 1,
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parameter CORE_TAG_WIDTH = 0,
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// size of tag id in core request tag
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parameter CORE_TAG_ID_BITS = 0
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@@ -172,21 +172,9 @@ module VX_bank #(
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assign reqq_push = core_req_ready && (| core_req_valids);
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VX_cache_req_queue #(
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.CACHE_SIZE (CACHE_SIZE),
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.BANK_LINE_SIZE (BANK_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQUESTS (NUM_REQUESTS),
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.STAGE_1_CYCLES (STAGE_1_CYCLES),
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.REQQ_SIZE (REQQ_SIZE),
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.MRVQ_SIZE (MRVQ_SIZE),
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.DFPQ_SIZE (DFPQ_SIZE),
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.SNRQ_SIZE (SNRQ_SIZE),
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.CWBQ_SIZE (CWBQ_SIZE),
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.DWBQ_SIZE (DWBQ_SIZE),
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.DFQQ_SIZE (DFQQ_SIZE),
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.LLVQ_SIZE (LLVQ_SIZE),
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.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
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.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS)
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) req_queue (
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@@ -363,17 +351,7 @@ module VX_bank #(
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.BANK_LINE_SIZE (BANK_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQUESTS (NUM_REQUESTS),
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.STAGE_1_CYCLES (STAGE_1_CYCLES),
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.REQQ_SIZE (REQQ_SIZE),
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.MRVQ_SIZE (MRVQ_SIZE),
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.DFPQ_SIZE (DFPQ_SIZE),
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.SNRQ_SIZE (SNRQ_SIZE),
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.CWBQ_SIZE (CWBQ_SIZE),
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.DWBQ_SIZE (DWBQ_SIZE),
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.DFQQ_SIZE (DFQQ_SIZE),
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.LLVQ_SIZE (LLVQ_SIZE),
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.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
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.DRAM_ENABLE (DRAM_ENABLE),
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.WRITE_ENABLE (WRITE_ENABLE)
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) tag_data_access (
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@@ -458,21 +436,11 @@ module VX_bank #(
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assign {miss_add_tag, miss_add_mem_read, miss_add_mem_write, miss_add_tid} = inst_meta_st2;
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VX_cache_miss_resrv #(
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.CACHE_SIZE (CACHE_SIZE),
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.BANK_LINE_SIZE (BANK_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQUESTS (NUM_REQUESTS),
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.STAGE_1_CYCLES (STAGE_1_CYCLES),
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.REQQ_SIZE (REQQ_SIZE),
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.MRVQ_SIZE (MRVQ_SIZE),
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.DFPQ_SIZE (DFPQ_SIZE),
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.SNRQ_SIZE (SNRQ_SIZE),
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.CWBQ_SIZE (CWBQ_SIZE),
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.DWBQ_SIZE (DWBQ_SIZE),
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.DFQQ_SIZE (DFQQ_SIZE),
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.LLVQ_SIZE (LLVQ_SIZE),
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.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
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.CORE_TAG_WIDTH (CORE_TAG_WIDTH)
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) cache_miss_resrv (
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.clk (clk),
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@@ -568,20 +536,8 @@ module VX_bank #(
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wire [`LINE_ADDR_WIDTH-1:0] fill_invalidator_addr = addr_st2;
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VX_fill_invalidator #(
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.CACHE_SIZE (CACHE_SIZE),
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.BANK_LINE_SIZE (BANK_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQUESTS (NUM_REQUESTS),
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.STAGE_1_CYCLES (STAGE_1_CYCLES),
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.REQQ_SIZE (REQQ_SIZE),
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.MRVQ_SIZE (MRVQ_SIZE),
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.DFPQ_SIZE (DFPQ_SIZE),
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.SNRQ_SIZE (SNRQ_SIZE),
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.CWBQ_SIZE (CWBQ_SIZE),
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.DWBQ_SIZE (DWBQ_SIZE),
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.DFQQ_SIZE (DFQQ_SIZE),
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.LLVQ_SIZE (LLVQ_SIZE),
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.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE)
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) fill_invalidator (
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.clk (clk),
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