From cc259f60f6f1c69c9e75d86cf0561c4e0836e7a0 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Wed, 11 Aug 2021 15:39:21 -0700 Subject: [PATCH] minor update --- .travis.yml | 14 +++++++------- ci/regression.sh | 24 ++++++++++++------------ hw/rtl/VX_cluster.v | 1 + hw/rtl/VX_lsu_unit.v | 7 ++++--- hw/rtl/VX_mem_unit.v | 1 + hw/rtl/afu/vortex_afu.sv | 6 ++++-- hw/scripts/scope.json | 8 +++----- 7 files changed, 32 insertions(+), 29 deletions(-) diff --git a/.travis.yml b/.travis.yml index e1644a83..6d1403c3 100644 --- a/.travis.yml +++ b/.travis.yml @@ -30,25 +30,25 @@ jobs: include: - stage: test name: coverage - script: cp -r $PWD ../build1 && cd ../build1 && ./ci/regression.sh -coverage + script: cp -r $PWD ../build1 && cd ../build1 && ./ci/travis_run.py ./ci/regression.sh -coverage - stage: test name: cluster - script: cp -r $PWD ../build2 && cd ../build2 && ./ci/regression.sh -cluster + script: cp -r $PWD ../build2 && cd ../build2 && ./ci/travis_run.py ./ci/regression.sh -cluster - stage: test name: debug - script: cp -r $PWD ../build3 && cd ../build3 && ./ci/regression.sh -debug + script: cp -r $PWD ../build3 && cd ../build3 && ./ci/travis_run.py ./ci/regression.sh -debug - stage: test name: config - script: cp -r $PWD ../build4 && cd ../build4 && ./ci/regression.sh -config + script: cp -r $PWD ../build4 && cd ../build4 && ./ci/travis_run.py ./ci/regression.sh -config - stage: test name: stress1 - script: cp -r $PWD ../build5 && cd ../build5 && ./ci/regression.sh -stress1 + script: cp -r $PWD ../build5 && cd ../build5 && ./ci/travis_run.py ./ci/regression.sh -stress1 - stage: test name: stress2 - script: cp -r $PWD ../build6 && cd ../build6 && ./ci/regression.sh -stress2 + script: cp -r $PWD ../build6 && cd ../build6 && ./ci/travis_run.py ./ci/regression.sh -stress2 - stage: test name: compiler - script: cp -r $PWD ../build7 && cd ../build7 && ./ci/test_compiler.sh + script: cp -r $PWD ../build7 && cd ../build7 && ./ci/travis_run.py /ci/test_compiler.sh after_success: # Gather code coverage diff --git a/ci/regression.sh b/ci/regression.sh index c591070c..72e076ec 100755 --- a/ci/regression.sh +++ b/ci/regression.sh @@ -27,17 +27,17 @@ cluster() echo "begin clustering tests..." # warp/threads configurations -./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=2 --threads=8 --app=demo -./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=8 --threads=2 --app=demo +./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=2 --threads=8 --app=demo +./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=8 --threads=2 --app=demo # cores clustering -./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=1 --clusters=1 --app=demo --args="-n1" -./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --app=demo --args="-n1" +./ci/blackbox.sh --driver=rtlsim --cores=1 --clusters=1 --app=demo --args="-n1" +./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --app=demo --args="-n1" # L2/L3 -./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=demo --args="-n1" -./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l3cache --app=demo --args="-n1" -./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l2cache --l3cache --app=io_addr --args="-n1" +./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=demo --args="-n1" +./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l3cache --app=demo --args="-n1" +./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l2cache --l3cache --app=io_addr --args="-n1" echo "clustering tests done!" } @@ -46,9 +46,9 @@ debug() { echo "begin debugging tests..." -./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --perf --app=demo --args="-n1" -./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --debug --app=demo --args="-n1" -./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --scope --app=basic --args="-t0 -n1" +./ci/blackbox.sh --driver=vlsim --cores=1 --perf --app=demo --args="-n1" +./ci/blackbox.sh --driver=vlsim --cores=1 --debug --app=demo --args="-n1" +./ci/blackbox.sh --driver=vlsim --cores=1 --scope --app=basic --args="-t0 -n1" echo "debugging tests done!" } @@ -106,7 +106,7 @@ stress1() { echo "begin stress tests..." -./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=sgemm --args="-n256" +./ci/blackbox.sh --driver=rtlsim --cores=1 --app=sgemm --args="-n256" echo "stress tests done!" } @@ -115,7 +115,7 @@ stress2() { echo "begin stress tests..." -./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --clusters=2 --l3cache --app=sgemm --args="-n256" +./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --clusters=2 --l3cache --app=sgemm --args="-n256" echo "stress tests done!" } diff --git a/hw/rtl/VX_cluster.v b/hw/rtl/VX_cluster.v index a8ed0870..56c70793 100644 --- a/hw/rtl/VX_cluster.v +++ b/hw/rtl/VX_cluster.v @@ -148,6 +148,7 @@ module VX_cluster #( .DATA_WIDTH (`L2MEM_DATA_WIDTH), .ADDR_WIDTH (`L2MEM_ADDR_WIDTH), .TAG_IN_WIDTH (`XMEM_TAG_WIDTH), + .TAG_SEL_IDX (1), // Skip 0 for NC flag .BUFFERED_REQ (1), .BUFFERED_RSP (1) ) mem_arb ( diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index a0d986dd..f8fbc104 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -306,7 +306,7 @@ module VX_lsu_unit #( `SCOPE_ASSIGN (dcache_rsp_tag, mbuf_raddr); `ifndef SYNTHESIS - reg [`LSUQ_SIZE-1:0][(`NW_BITS + 32 + 64 + 1)-1:0] pending_reqs; + reg [`LSUQ_SIZE-1:0][(`NW_BITS + 32 + `NR_BITS + 64 + 1)-1:0] pending_reqs; wire [63:0] delay_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE)); always @(posedge clk) begin @@ -314,7 +314,7 @@ module VX_lsu_unit #( pending_reqs <= '0; end begin if (mbuf_push) begin - pending_reqs[mbuf_waddr] <= {req_wid, req_pc, $time, 1'b1}; + pending_reqs[mbuf_waddr] <= {req_wid, req_pc, req_rd, $time, 1'b1}; end if (mbuf_pop) begin pending_reqs[mbuf_raddr] <= '0; @@ -324,7 +324,8 @@ module VX_lsu_unit #( for (integer i = 0; i < `LSUQ_SIZE; ++i) begin if (pending_reqs[i][0]) begin assert(($time - pending_reqs[i][1 +: 64]) < delay_timeout) else - $error("%t: *** D$%0d response timeout: wid=%0d, PC=%0h", $time, CORE_ID, pending_reqs[i][1+64+32 +: `NW_BITS], pending_reqs[i][1+64 +: 32]); + $error("%t: *** D$%0d response timeout: remaining=%b, wid=%0d, PC=%0h, rd=%0d", $time, CORE_ID, + rsp_rem_mask[i], pending_reqs[i][1+64+32+`NR_BITS +: `NW_BITS], pending_reqs[i][1+64+`NR_BITS +: 32], pending_reqs[i][1+64 +: `NR_BITS]); end end end diff --git a/hw/rtl/VX_mem_unit.v b/hw/rtl/VX_mem_unit.v index 7cb071db..c68e051a 100644 --- a/hw/rtl/VX_mem_unit.v +++ b/hw/rtl/VX_mem_unit.v @@ -307,6 +307,7 @@ module VX_mem_unit # ( .DATA_WIDTH (`DMEM_DATA_WIDTH), .ADDR_WIDTH (`DMEM_ADDR_WIDTH), .TAG_IN_WIDTH (`DMEM_TAG_WIDTH), + .TAG_SEL_IDX (1), // Skip 0 for NC flag .BUFFERED_REQ (1), .BUFFERED_RSP (2) ) mem_arb ( diff --git a/hw/rtl/afu/vortex_afu.sv b/hw/rtl/afu/vortex_afu.sv index 4502d180..b10fb062 100644 --- a/hw/rtl/afu/vortex_afu.sv +++ b/hw/rtl/afu/vortex_afu.sv @@ -46,8 +46,10 @@ localparam CCI_DATA_SIZE = CCI_DATA_WIDTH / 8; localparam CCI_ADDR_WIDTH = 32 - $clog2(CCI_DATA_SIZE); localparam AVS_RD_QUEUE_SIZE = 4; -localparam AVS_REQ_TAGW_VX = `MAX(`VX_MEM_TAG_WIDTH, `VX_MEM_TAG_WIDTH + $clog2(LMEM_DATA_WIDTH) - $clog2(`VX_MEM_DATA_WIDTH)); -localparam AVS_REQ_TAGW_CCI = `MAX(CCI_ADDR_WIDTH, CCI_ADDR_WIDTH + $clog2(LMEM_DATA_WIDTH) - $clog2(CCI_DATA_WIDTH)); +localparam AVS_REQ_TAGW_VX_ = `VX_MEM_TAG_WIDTH + $clog2(LMEM_DATA_WIDTH) - $clog2(`VX_MEM_DATA_WIDTH); +localparam AVS_REQ_TAGW_VX = `MAX(`VX_MEM_TAG_WIDTH, AVS_REQ_TAGW_VX_); +localparam AVS_REQ_TAGW_CCI_ = CCI_ADDR_WIDTH + $clog2(LMEM_DATA_WIDTH) - $clog2(CCI_DATA_WIDTH); +localparam AVS_REQ_TAGW_CCI = `MAX(CCI_ADDR_WIDTH, AVS_REQ_TAGW_CCI_); localparam AVS_REQ_TAGW = `MAX(AVS_REQ_TAGW_VX, AVS_REQ_TAGW_CCI); localparam CCI_RD_WINDOW_SIZE = 8; diff --git a/hw/scripts/scope.json b/hw/scripts/scope.json index 338912b8..7d7190b0 100644 --- a/hw/scripts/scope.json +++ b/hw/scripts/scope.json @@ -111,9 +111,9 @@ "!cci_pending_writes_full": 1, "?afu_mem_req_fire": 1, "afu_mem_req_addr": 26, - "afu_mem_req_tag": 29, + "afu_mem_req_tag": 32, "?afu_mem_rsp_fire": 1, - "afu_mem_rsp_tag": 29 + "afu_mem_rsp_tag": 32 }, "afu/vortex": { "!reset": 1, @@ -203,9 +203,7 @@ "is_fill_st0": 1, "is_mshr_st0": 1, "miss_st0": 1, - "force_miss_st0": 1, - "mshr_push": 1, - "?crsq_in_stall": 1, + "?crsq_stall": 1, "?mreq_alm_full": 1, "?mshr_alm_full": 1 }