better use of valid signal

2019-03-27 00:07:59 -04:00
parent 7a528c5ef2
commit cc0fb0eece
23 changed files with 171 additions and 160 deletions
--- a/rtl/VX_register_file.v
+++ b/rtl/VX_register_file.v
@@ -2,6 +2,7 @@

 module VX_register_file (
  input wire        clk,
+  input wire        in_valid,
  input wire        in_write_register,
  input wire[4:0]   in_rd,
  input wire[31:0]  in_data,
@@ -30,7 +31,7 @@ module VX_register_file (
 	assign write_data     = in_data;
 	assign write_register = in_rd;

-	assign write_enable   = in_write_register && (in_rd != 5'h0);
+	assign write_enable   = in_write_register && (in_rd != 5'h0) && in_valid;

 	always @(posedge clk) begin
 		if(write_enable) begin