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Add Blackwell tensor RTL scaffolding

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This commit is contained in:
abnerhexu
2026-04-25 10:15:31 +08:00
parent f1d0fac518
commit cb912d3b8b
13 changed files with 281 additions and 34 deletions
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14
hw/rtl/core/VX_decode.sv
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@@ -555,6 +555,20 @@ module VX_decode #(
// B matrix tiles
`USED_IREG (rs1);
`USED_IREG (rs2);
`elsif EXT_T_BLACKWELL
ex_type = `EX_TENSOR;
case (func3)
3'b000: op_type = `INST_TENSOR_BWGMMA;
3'b001: op_type = `INST_TENSOR_BWGMMA_WAIT;
3'b010: op_type = `INST_TENSOR_TCGEN05_CP;
3'b011: op_type = `INST_TENSOR_TCGEN05_CP_WAIT;
3'b100: op_type = `INST_TENSOR_TCGEN05_LD;
3'b101: op_type = `INST_TENSOR_TCGEN05_ST;
default: ;
endcase
`USED_IREG (rd);
`USED_IREG (rs1);
`USED_IREG (rs2);
`else
ex_type = `EX_TENSOR;
op_type = `INST_TENSOR_HMMA;