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fix quartus build

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This commit is contained in:
Blaise Tine
2020-04-21 00:55:18 -07:00
parent d6255f0445
commit cb0afd3eec
6 changed files with 67 additions and 80 deletions
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2
hw/rtl/VX_gpr.v
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@@ -15,7 +15,7 @@ module VX_gpr (
`ifndef ASIC `ifndef ASIC
assign write_enable = valid_write_request && ((writeback_if.wb != 0)) && (writeback_if.rd != 0); assign write_enable = valid_write_request && ((writeback_if.wb != 0)) && (writeback_if.rd != 0);
byte_enabled_simple_dual_port_ram first_ram( VX_byte_enabled_dual_port_ram be_dp_ram (
.we (write_enable), .we (write_enable),
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

53
hw/rtl/byte_enabled_simple_dual_port_ram.v
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@@ -1,53 +0,0 @@
`include "VX_define.vh"
module byte_enabled_simple_dual_port_ram
(
input clk;
input wire reset;
input wire we;
input wire[4:0] waddr,
input wire[4:0] raddr1,
input wire[4:0] raddr2,
input wire[`NUM_THREADS-1:0] be,
input wire[`NUM_THREADS-1:0][31:0] wdata,
output reg[`NUM_THREADS-1:0][31:0] q1
output reg[`NUM_THREADS-1:0][31:0] q2
);
// integer regi;
// integer threadi;
// Thread Byte Bit
logic [`NUM_THREADS-1:0][3:0][7:0] GPR[31:0];
always @(posedge clk) begin
if (reset) begin
//--
end else begin
if (we) begin
integer thread_ind;
for (thread_ind = 0; thread_ind < `NUM_THREADS; thread_ind = thread_ind + 1) begin
if (be[thread_ind]) begin
GPR[waddr][thread_ind][0] <= wdata[thread_ind][7:0];
GPR[waddr][thread_ind][1] <= wdata[thread_ind][15:8];
GPR[waddr][thread_ind][2] <= wdata[thread_ind][23:16];
GPR[waddr][thread_ind][3] <= wdata[thread_ind][31:24];
end
end
end
// $display("^^^^^^^^^^^^^^^^^^^^^^^");
// for (regi = 0; regi <= 31; regi = regi + 1) begin
// for (threadi = 0; threadi < `NUM_THREADS; threadi = threadi + 1) begin
// if (GPR[regi][threadi] != 0) $display("$%d: %h",regi, GPR[regi][threadi]);
// end
// end
end
end
assign q1 = GPR[raddr1];
assign q2 = GPR[raddr2];
// assign q1 = (raddr1 == waddr && (we)) ? wdata : GPR[raddr1];
// assign q2 = (raddr2 == waddr && (we)) ? wdata : GPR[raddr2];
endmodule

51
hw/rtl/libs/VX_byte_enabled_dual_port_ram.v Normal file
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@@ -0,0 +1,51 @@
`include "VX_define.vh"
module VX_byte_enabled_dual_port_ram (
input wire clk,
input wire reset,
input wire we,
input wire [4:0] waddr,
input wire [4:0] raddr1,
input wire [4:0] raddr2,
input wire [`NUM_THREADS-1:0] be,
input wire [`NUM_THREADS-1:0][31:0] wdata,
output reg [`NUM_THREADS-1:0][31:0] q1,
output reg [`NUM_THREADS-1:0][31:0] q2
);
// integer regi;
// integer threadi;
// Thread Byte Bit
logic [`NUM_THREADS-1:0][3:0][7:0] ram[31:0];
always @(posedge clk) begin
if (reset) begin
//--
end else begin
if (we) begin
integer thread_ind;
for (thread_ind = 0; thread_ind < `NUM_THREADS; thread_ind = thread_ind + 1) begin
if (be[thread_ind]) begin
ram[waddr][thread_ind][0] <= wdata[thread_ind][7:0];
ram[waddr][thread_ind][1] <= wdata[thread_ind][15:8];
ram[waddr][thread_ind][2] <= wdata[thread_ind][23:16];
ram[waddr][thread_ind][3] <= wdata[thread_ind][31:24];
end
end
end
// $display("^^^^^^^^^^^^^^^^^^^^^^^");
// for (regi = 0; regi <= 31; regi = regi + 1) begin
// for (threadi = 0; threadi < `NUM_THREADS; threadi = threadi + 1) begin
// if (ram[regi][threadi] != 0) $display("$%d: %h",regi, ram[regi][threadi]);
// end
// end
end
end
assign q1 = ram[raddr1];
assign q2 = ram[raddr2];
// assign q1 = (raddr1 == waddr && (we)) ? wdata : ram[raddr1];
// assign q2 = (raddr2 == waddr && (we)) ? wdata : ram[raddr2];
endmodule

6
hw/rtl/libs/VX_mult.v
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@@ -9,9 +9,9 @@ module VX_mult #(
parameter PIPELINE=0, parameter PIPELINE=0,
parameter FORCE_LE="NO" parameter FORCE_LE="NO"
) ( ) (
input clock; input clock,
input aclr; input aclr,
input clken; input clken,
input [WIDTHA-1:0] dataa, input [WIDTHA-1:0] dataa,
input [WIDTHB-1:0] datab, input [WIDTHB-1:0] datab,

4
hw/syn/quartus/cache/Makefile vendored
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@@ -1,6 +1,6 @@
PROJECT = VX_cache PROJECT = VX_cache
TOP_LEVEL_ENTITY = VX_cache TOP_LEVEL_ENTITY = VX_cache
SRC_FILE = ../../../rtl/cache/VX_cache.v SRC_FILE = VX_cache.v
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
# Part, Family # Part, Family
@@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization # Project initialization
$(PROJECT_FILES): $(PROJECT_FILES):
quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../;../../" quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache"
syn.chg: syn.chg:
$(STAMP) syn.chg $(STAMP) syn.chg

31
hw/syn/quartus/top/Makefile
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@@ -1,10 +1,8 @@
PROJECT = Vortex PROJECT = Vortex
TOP_LEVEL_ENTITY = Vortex_Socket TOP_LEVEL_ENTITY = Vortex
SRC_FILE = ../../../rtl/Vortex.v SRC_FILE = Vortex.v
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
QUARTUS_ROOT ?= /tools/reconfig/intel/18.0
# Part, Family # Part, Family
FAMILY = "Arria 10" FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG DEVICE = 10AX115N3F40E2SG
@@ -16,7 +14,7 @@ ASM_ARGS =
STA_ARGS = --do_report_timing STA_ARGS = --do_report_timing
# Build targets # Build targets
all: $(PROJECT).sta.rpt $(PROJECT).pow.rpt all: $(PROJECT).sta.rpt
syn: $(PROJECT).syn.rpt syn: $(PROJECT).syn.rpt
@@ -26,38 +24,32 @@ asm: $(PROJECT).asm.rpt
sta: $(PROJECT).sta.rpt sta: $(PROJECT).sta.rpt
pow: $(PROJECT).pow.rpt
smart: smart.log smart: smart.log
# Target implementations # Target implementations
STAMP = echo done > STAMP = echo done >
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) $(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
$(QUARTUS_ROOT)/quartus/bin/quartus_syn $(PROJECT) $(SYN_ARGS) quartus_syn $(PROJECT) $(SYN_ARGS)
$(STAMP) fit.chg $(STAMP) fit.chg
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt $(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
$(QUARTUS_ROOT)/quartus/bin/quartus_fit $(PROJECT) $(FIT_ARGS) quartus_fit $(PROJECT) $(FIT_ARGS)
$(STAMP) asm.chg $(STAMP) asm.chg
$(STAMP) sta.chg $(STAMP) sta.chg
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt $(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
$(QUARTUS_ROOT)/quartus/bin/quartus_asm $(PROJECT) $(ASM_ARGS) quartus_asm $(PROJECT) $(ASM_ARGS)
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt $(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
$(QUARTUS_ROOT)/quartus/bin/quartus_sta $(PROJECT) $(STA_ARGS) quartus_sta $(PROJECT) $(STA_ARGS)
$(QUARTUS_ROOT)/quartus/bin/quartus_sta -t VX_timing.tcl
$(PROJECT).pow.rpt: smart.log pow.chg $(PROJECT).fit.rpt
$(QUARTUS_ROOT)/quartus/bin/quartus_pow $(PROJECT)
smart.log: $(PROJECT_FILES) smart.log: $(PROJECT_FILES)
$(QUARTUS_ROOT)/quartus/bin/quartus_sh --determine_smart_action $(PROJECT) > smart.log quartus_sh --determine_smart_action $(PROJECT) > smart.log
# Project initialization # Project initialization
$(PROJECT_FILES): $(PROJECT_FILES):
$(QUARTUS_ROOT)/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc vortex.sdc -inc "..;../libs;../interfaces;../pipe_regs;../cache" quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache"
syn.chg: syn.chg:
$(STAMP) syn.chg $(STAMP) syn.chg
@@ -71,11 +63,8 @@ sta.chg:
asm.chg: asm.chg:
$(STAMP) asm.chg $(STAMP) asm.chg
pow.chg:
$(STAMP) pow.chg
program: $(PROJECT).sof program: $(PROJECT).sof
$(QUARTUS_ROOT)/quartus/bin/quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof" quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
clean: clean:
rm -rf bin *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox rm -rf bin *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox