From ca61801199ebaf0b5f01b05d26cfeaedd12a377c Mon Sep 17 00:00:00 2001
From: wgulian3 <wgulian@gatech.edu>
Date: Sat, 22 Feb 2020 20:16:13 -0500
Subject: [PATCH] Make ALU div/mul pipelines longer and support logic element
 multiplication mode for better long pipeline performance

---
 rtl/VX_alu.v         |  5 ++--
 rtl/compat/VX_mult.v | 59 ++++++++++++++++++++++++++++++--------------
 2 files changed, 43 insertions(+), 21 deletions(-)

diff --git a/rtl/VX_alu.v b/rtl/VX_alu.v
index 1415aef3..53b05b2d 100644
--- a/rtl/VX_alu.v
+++ b/rtl/VX_alu.v
@@ -14,8 +14,8 @@ module VX_alu(
 	output reg        out_alu_stall
 	);
 
-		localparam div_pipeline_len = 10;
-		localparam mul_pipeline_len = 3;
+		localparam div_pipeline_len = 20;
+		localparam mul_pipeline_len = 8;
 
 		wire[31:0] unsigned_div_result;
         wire[31:0] unsigned_rem_result;
@@ -62,6 +62,7 @@ module VX_alu(
 			.WIDTHB(64),
 			.WIDTHP(64),
 			.SPEED("HIGHEST"),
+			.FORCE_LE("YES"),
 			.PIPELINE(mul_pipeline_len)
 		) multiplier (
 			.clock(clk),
diff --git a/rtl/compat/VX_mult.v b/rtl/compat/VX_mult.v
index c1f14c0e..f9a07543 100644
--- a/rtl/compat/VX_mult.v
+++ b/rtl/compat/VX_mult.v
@@ -5,7 +5,8 @@ module VX_mult
         parameter WIDTHP=1,
         parameter REP="UNSIGNED",
         parameter SPEED="MIXED", // "MIXED" or "HIGHEST"
-        parameter PIPELINE=0
+        parameter PIPELINE=0,
+        parameter FORCE_LE="NO"
     )
     (
         input clock, aclr, clken,
@@ -30,21 +31,41 @@ module VX_mult
 
             localparam lpm_speed=SPEED == "HIGHEST" ? 10:5;
 
-            lpm_mult#(
-                .LPM_WIDTHA(WIDTHA),
-                .LPM_WIDTHB(WIDTHB),
-                .LPM_WIDTHP(WIDTHP),
-                .LPM_REPRESENTATION(REP),
-                .LPM_PIPELINE(PIPELINE),
-                .MAXIMIZE_SPEED(lpm_speed)
-            ) quartus_mult(
-                .clock(clock),
-                .aclr(aclr),
-                .clken(clken),
-                .dataa(dataa),
-                .datab(datab),
-                .result(result)
-            );
+            if (FORCE_LE == "YES") begin
+                lpm_mult#(
+                    .LPM_WIDTHA(WIDTHA),
+                    .LPM_WIDTHB(WIDTHB),
+                    .LPM_WIDTHP(WIDTHP),
+                    .LPM_REPRESENTATION(REP),
+                    .LPM_PIPELINE(PIPELINE),
+                    .DSP_BLOCK_BALANCING("LOGIC ELEMENTS"),
+                    .MAXIMIZE_SPEED(lpm_speed)
+                ) quartus_mult(
+                    .clock(clock),
+                    .aclr(aclr),
+                    .clken(clken),
+                    .dataa(dataa),
+                    .datab(datab),
+                    .result(result)
+                );
+            end
+            else begin
+                lpm_mult#(
+                    .LPM_WIDTHA(WIDTHA),
+                    .LPM_WIDTHB(WIDTHB),
+                    .LPM_WIDTHP(WIDTHP),
+                    .LPM_REPRESENTATION(REP),
+                    .LPM_PIPELINE(PIPELINE),
+                    .MAXIMIZE_SPEED(lpm_speed)
+                ) quartus_mult(
+                    .clock(clock),
+                    .aclr(aclr),
+                    .clken(clken),
+                    .dataa(dataa),
+                    .datab(datab),
+                    .result(result)
+                );
+            end
 
         end
         else begin
@@ -92,13 +113,13 @@ module VX_mult
             /* * * * * * * * * * * * * * * * * * * * * * */
 
             if (REP == "SIGNED") begin
-                assign result = $signed($signed(dataa_pipe_end) * $signed(datab_pipe_end));
+                assign result = $signed($signed(dataa_pipe_end)*$signed(datab_pipe_end));
             end
             else begin
-                assign result = dataa_pipe_end * datab_pipe_end;
+                assign result = dataa_pipe_end*datab_pipe_end;
             end
 
         end
     endgenerate
 
-endmodule : VX_mult
+endmodule: VX_mult