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OUTPUT_REG => OUT_REG renaming

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This commit is contained in:
Blaise Tine
2021-09-09 03:05:38 -07:00
parent a25076b9c1
commit ca46b0a0be
14 changed files with 62 additions and 62 deletions
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6
hw/rtl/VX_ibuffer.v
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@@ -38,9 +38,9 @@ module VX_ibuffer #(
wire going_empty = empty_r[i] || (alm_empty_r[i] && reading); wire going_empty = empty_r[i] || (alm_empty_r[i] && reading);
VX_elastic_buffer #( VX_elastic_buffer #(
.DATAW (DATAW), .DATAW (DATAW),
.SIZE (`IBUF_SIZE), .SIZE (`IBUF_SIZE),
.OUTPUT_REG (1) .OUT_REG (1)
) queue ( ) queue (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

6
hw/rtl/VX_icache_stage.v
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@@ -22,7 +22,7 @@ module VX_icache_stage #(
`UNUSED_PARAM (CORE_ID) `UNUSED_PARAM (CORE_ID)
`UNUSED_VAR (reset) `UNUSED_VAR (reset)
localparam OUTPUT_REG = 0; localparam OUT_REG = 0;
wire icache_req_fire = icache_req_if.valid && icache_req_if.ready; wire icache_req_fire = icache_req_if.valid && icache_req_if.ready;
@@ -64,12 +64,12 @@ module VX_icache_stage #(
wire [`NW_BITS-1:0] rsp_wid = rsp_tag; wire [`NW_BITS-1:0] rsp_wid = rsp_tag;
wire stall_out = ~ifetch_rsp_if.ready && (0 == OUTPUT_REG && ifetch_rsp_if.valid); wire stall_out = ~ifetch_rsp_if.ready && (0 == OUT_REG && ifetch_rsp_if.valid);
VX_pipe_register #( VX_pipe_register #(
.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + 32), .DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + 32),
.RESETW (1), .RESETW (1),
.DEPTH (OUTPUT_REG) .DEPTH (OUT_REG)
) pipe_reg ( ) pipe_reg (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

16
hw/rtl/afu/VX_avs_wrapper.v
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@@ -42,7 +42,7 @@ module VX_avs_wrapper #(
); );
localparam BANK_ADDRW = `LOG2UP(AVS_BANKS); localparam BANK_ADDRW = `LOG2UP(AVS_BANKS);
localparam OUTPUT_REG = (AVS_BANKS > 2); localparam OUT_REG = (AVS_BANKS > 2);
// Requests handling // Requests handling
@@ -78,9 +78,9 @@ module VX_avs_wrapper #(
`UNUSED_VAR (req_queue_size) `UNUSED_VAR (req_queue_size)
VX_fifo_queue #( VX_fifo_queue #(
.DATAW (REQ_TAG_WIDTH), .DATAW (REQ_TAG_WIDTH),
.SIZE (RD_QUEUE_SIZE), .SIZE (RD_QUEUE_SIZE),
.OUTPUT_REG (!OUTPUT_REG) .OUT_REG (!OUT_REG)
) rd_req_queue ( ) rd_req_queue (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -122,9 +122,9 @@ module VX_avs_wrapper #(
for (genvar i = 0; i < AVS_BANKS; i++) begin for (genvar i = 0; i < AVS_BANKS; i++) begin
VX_fifo_queue #( VX_fifo_queue #(
.DATAW (AVS_DATA_WIDTH), .DATAW (AVS_DATA_WIDTH),
.SIZE (RD_QUEUE_SIZE), .SIZE (RD_QUEUE_SIZE),
.OUTPUT_REG (!OUTPUT_REG) .OUT_REG (!OUT_REG)
) rd_rsp_queue ( ) rd_rsp_queue (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -150,7 +150,7 @@ module VX_avs_wrapper #(
.NUM_REQS (AVS_BANKS), .NUM_REQS (AVS_BANKS),
.DATAW (AVS_DATA_WIDTH + REQ_TAG_WIDTH), .DATAW (AVS_DATA_WIDTH + REQ_TAG_WIDTH),
.TYPE ("R"), .TYPE ("R"),
.BUFFERED (OUTPUT_REG ? 1 : 0) .BUFFERED (OUT_REG ? 1 : 0)
) rsp_arb ( ) rsp_arb (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

10
hw/rtl/afu/vortex_afu.sv
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@@ -520,8 +520,8 @@ VX_mem_arb #(
.ADDR_WIDTH (LMEM_ADDR_WIDTH), .ADDR_WIDTH (LMEM_ADDR_WIDTH),
.TAG_IN_WIDTH (AVS_REQ_TAGW), .TAG_IN_WIDTH (AVS_REQ_TAGW),
.TYPE ("P"), .TYPE ("P"),
.BUFFERED_REQ (0), .BUFFERED_REQ (1),
.BUFFERED_RSP (0) .BUFFERED_RSP (1)
) mem_arb ( ) mem_arb (
.clk (clk), .clk (clk),
.reset (mem_arb_reset), .reset (mem_arb_reset),
@@ -731,9 +731,9 @@ end
`RESET_RELAY (cci_rdq_reset); `RESET_RELAY (cci_rdq_reset);
VX_fifo_queue #( VX_fifo_queue #(
.DATAW (CCI_RD_QUEUE_DATAW), .DATAW (CCI_RD_QUEUE_DATAW),
.SIZE (CCI_RD_QUEUE_SIZE), .SIZE (CCI_RD_QUEUE_SIZE),
.OUTPUT_REG (1) .OUT_REG (1)
) cci_rd_req_queue ( ) cci_rd_req_queue (
.clk (clk), .clk (clk),
.reset (cci_rdq_reset), .reset (cci_rdq_reset),

6
hw/rtl/cache/VX_bank.v vendored
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@@ -465,9 +465,9 @@ module VX_bank #(
end end
VX_elastic_buffer #( VX_elastic_buffer #(
.DATAW (NUM_PORTS * (CORE_TAG_WIDTH + 1 + `WORD_WIDTH + `REQS_BITS)), .DATAW (NUM_PORTS * (CORE_TAG_WIDTH + 1 + `WORD_WIDTH + `REQS_BITS)),
.SIZE (CRSQ_SIZE), .SIZE (CRSQ_SIZE),
.OUTPUT_REG (1 == NUM_BANKS) .OUT_REG (1 == NUM_BANKS)
) core_rsp_req ( ) core_rsp_req (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

6
hw/rtl/cache/VX_cache.v vendored
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@@ -314,9 +314,9 @@ module VX_cache #(
`RESET_RELAY (mrsq_reset); `RESET_RELAY (mrsq_reset);
VX_elastic_buffer #( VX_elastic_buffer #(
.DATAW (MEM_TAG_IN_WIDTH + `CACHE_LINE_WIDTH), .DATAW (MEM_TAG_IN_WIDTH + `CACHE_LINE_WIDTH),
.SIZE (MRSQ_SIZE), .SIZE (MRSQ_SIZE),
.OUTPUT_REG (MRSQ_SIZE > 2) .OUT_REG (MRSQ_SIZE > 2)
) mem_rsp_queue ( ) mem_rsp_queue (
.clk (clk), .clk (clk),
.reset (mrsq_reset), .reset (mrsq_reset),

6
hw/rtl/cache/VX_shared_mem.v vendored
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@@ -127,9 +127,9 @@ module VX_shared_mem #(
assign core_req_writeonly_unqual = ~(| core_req_read_mask_unqual); assign core_req_writeonly_unqual = ~(| core_req_read_mask_unqual);
VX_elastic_buffer #( VX_elastic_buffer #(
.DATAW (NUM_BANKS * (1 + 1 + `LINE_ADDR_WIDTH + WORD_SIZE + `WORD_WIDTH + CORE_TAG_WIDTH + `REQS_BITS) + NUM_BANKS + 1), .DATAW (NUM_BANKS * (1 + 1 + `LINE_ADDR_WIDTH + WORD_SIZE + `WORD_WIDTH + CORE_TAG_WIDTH + `REQS_BITS) + NUM_BANKS + 1),
.SIZE (CREQ_SIZE), .SIZE (CREQ_SIZE),
.OUTPUT_REG (1) // output should be registered for the data_store addr port .OUT_REG (1) // output should be registered for the data_store addr port
) core_req_queue ( ) core_req_queue (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

8
hw/rtl/libs/VX_dp_ram.v
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@@ -5,7 +5,7 @@ module VX_dp_ram #(
parameter DATAW = 1, parameter DATAW = 1,
parameter SIZE = 1, parameter SIZE = 1,
parameter BYTEENW = 1, parameter BYTEENW = 1,
parameter OUTPUT_REG = 0, parameter OUT_REG = 0,
parameter NO_RWCHECK = 0, parameter NO_RWCHECK = 0,
parameter ADDRW = $clog2(SIZE), parameter ADDRW = $clog2(SIZE),
parameter LUTRAM = 0, parameter LUTRAM = 0,
@@ -35,7 +35,7 @@ module VX_dp_ram #(
`ifdef SYNTHESIS `ifdef SYNTHESIS
if (LUTRAM) begin if (LUTRAM) begin
if (OUTPUT_REG) begin if (OUT_REG) begin
reg [DATAW-1:0] rdata_r; reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
@@ -90,7 +90,7 @@ module VX_dp_ram #(
end end
end end
end else begin end else begin
if (OUTPUT_REG) begin if (OUT_REG) begin
reg [DATAW-1:0] rdata_r; reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
@@ -173,7 +173,7 @@ module VX_dp_ram #(
end end
end end
`else `else
if (OUTPUT_REG) begin if (OUT_REG) begin
reg [DATAW-1:0] rdata_r; reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];

14
hw/rtl/libs/VX_elastic_buffer.v
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@@ -4,7 +4,7 @@
module VX_elastic_buffer #( module VX_elastic_buffer #(
parameter DATAW = 1, parameter DATAW = 1,
parameter SIZE = 2, parameter SIZE = 2,
parameter OUTPUT_REG = 0, parameter OUT_REG = 0,
parameter LUTRAM = 0 parameter LUTRAM = 0
) ( ) (
input wire clk, input wire clk,
@@ -32,8 +32,8 @@ module VX_elastic_buffer #(
end else if (SIZE == 2) begin end else if (SIZE == 2) begin
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (DATAW), .DATAW (DATAW),
.OUTPUT_REG (OUTPUT_REG) .OUT_REG (OUT_REG)
) queue ( ) queue (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -53,10 +53,10 @@ module VX_elastic_buffer #(
wire pop = valid_out && ready_out; wire pop = valid_out && ready_out;
VX_fifo_queue #( VX_fifo_queue #(
.DATAW (DATAW), .DATAW (DATAW),
.SIZE (SIZE), .SIZE (SIZE),
.OUTPUT_REG (OUTPUT_REG), .OUT_REG (OUT_REG),
.LUTRAM (LUTRAM) .LUTRAM (LUTRAM)
) queue ( ) queue (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

22
hw/rtl/libs/VX_fifo_queue.v
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@@ -8,7 +8,7 @@ module VX_fifo_queue #(
parameter ALM_EMPTY = 1, parameter ALM_EMPTY = 1,
parameter ADDRW = $clog2(SIZE), parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1), parameter SIZEW = $clog2(SIZE+1),
parameter OUTPUT_REG = 0, parameter OUT_REG = 0,
parameter LUTRAM = 1 parameter LUTRAM = 1
) ( ) (
input wire clk, input wire clk,
@@ -103,7 +103,7 @@ module VX_fifo_queue #(
if (SIZE == 2) begin if (SIZE == 2) begin
if (0 == OUTPUT_REG) begin if (0 == OUT_REG) begin
reg [DATAW-1:0] shift_reg [1:0]; reg [DATAW-1:0] shift_reg [1:0];
@@ -138,7 +138,7 @@ module VX_fifo_queue #(
end else begin end else begin
if (0 == OUTPUT_REG) begin if (0 == OUT_REG) begin
reg [ADDRW-1:0] rd_ptr_r; reg [ADDRW-1:0] rd_ptr_r;
reg [ADDRW-1:0] wr_ptr_r; reg [ADDRW-1:0] wr_ptr_r;
@@ -154,10 +154,10 @@ module VX_fifo_queue #(
end end
VX_dp_ram #( VX_dp_ram #(
.DATAW (DATAW), .DATAW (DATAW),
.SIZE (SIZE), .SIZE (SIZE),
.OUTPUT_REG (0), .OUT_REG (0),
.LUTRAM (LUTRAM) .LUTRAM (LUTRAM)
) dp_ram ( ) dp_ram (
.clk(clk), .clk(clk),
.wren (push), .wren (push),
@@ -197,10 +197,10 @@ module VX_fifo_queue #(
end end
VX_dp_ram #( VX_dp_ram #(
.DATAW (DATAW), .DATAW (DATAW),
.SIZE (SIZE), .SIZE (SIZE),
.OUTPUT_REG (0), .OUT_REG (0),
.LUTRAM (LUTRAM) .LUTRAM (LUTRAM)
) dp_ram ( ) dp_ram (
.clk (clk), .clk (clk),
.wren (push), .wren (push),

4
hw/rtl/libs/VX_skid_buffer.v
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@@ -5,7 +5,7 @@ module VX_skid_buffer #(
parameter DATAW = 1, parameter DATAW = 1,
parameter PASSTHRU = 0, parameter PASSTHRU = 0,
parameter NOBACKPRESSURE = 0, parameter NOBACKPRESSURE = 0,
parameter OUTPUT_REG = 0 parameter OUT_REG = 0
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,
@@ -51,7 +51,7 @@ module VX_skid_buffer #(
end else begin end else begin
if (OUTPUT_REG) begin if (OUT_REG) begin
reg [DATAW-1:0] data_out_r; reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] buffer; reg [DATAW-1:0] buffer;

8
hw/rtl/libs/VX_sp_ram.v
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@@ -5,7 +5,7 @@ module VX_sp_ram #(
parameter DATAW = 1, parameter DATAW = 1,
parameter SIZE = 1, parameter SIZE = 1,
parameter BYTEENW = 1, parameter BYTEENW = 1,
parameter OUTPUT_REG = 0, parameter OUT_REG = 0,
parameter NO_RWCHECK = 0, parameter NO_RWCHECK = 0,
parameter ADDRW = $clog2(SIZE), parameter ADDRW = $clog2(SIZE),
parameter LUTRAM = 0, parameter LUTRAM = 0,
@@ -34,7 +34,7 @@ module VX_sp_ram #(
`ifdef SYNTHESIS `ifdef SYNTHESIS
if (LUTRAM) begin if (LUTRAM) begin
if (OUTPUT_REG) begin if (OUT_REG) begin
reg [DATAW-1:0] rdata_r; reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
@@ -90,7 +90,7 @@ module VX_sp_ram #(
end end
end end
end else begin end else begin
if (OUTPUT_REG) begin if (OUT_REG) begin
reg [DATAW-1:0] rdata_r; reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
@@ -173,7 +173,7 @@ module VX_sp_ram #(
end end
end end
`else `else
if (OUTPUT_REG) begin if (OUT_REG) begin
reg [DATAW-1:0] rdata_r; reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];

6
hw/rtl/libs/VX_stream_arbiter.v
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@@ -132,9 +132,9 @@ module VX_stream_arbiter #(
for (genvar i = 0; i < LANES; ++i) begin for (genvar i = 0; i < LANES; ++i) begin
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (DATAW), .DATAW (DATAW),
.PASSTHRU (0 == BUFFERED), .PASSTHRU (0 == BUFFERED),
.OUTPUT_REG (2 == BUFFERED) .OUT_REG (2 == BUFFERED)
) out_buffer ( ) out_buffer (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

6
hw/rtl/libs/VX_stream_demux.v
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@@ -37,9 +37,9 @@ module VX_stream_demux #(
for (genvar i = 0; i < NUM_REQS; i++) begin for (genvar i = 0; i < NUM_REQS; i++) begin
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (DATAW), .DATAW (DATAW),
.PASSTHRU (0 == BUFFERED), .PASSTHRU (0 == BUFFERED),
.OUTPUT_REG (2 == BUFFERED) .OUT_REG (2 == BUFFERED)
) out_buffer ( ) out_buffer (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),