OUTPUT_REG => OUT_REG renaming

2021-09-09 03:05:38 -07:00
parent a25076b9c1
commit ca46b0a0be
14 changed files with 62 additions and 62 deletions
--- a/hw/rtl/libs/VX_stream_demux.v
+++ b/hw/rtl/libs/VX_stream_demux.v
@@ -37,9 +37,9 @@ module VX_stream_demux #(

            for (genvar i = 0; i < NUM_REQS; i++) begin
                VX_skid_buffer #(
-                    .DATAW      (DATAW),
-                    .PASSTHRU   (0 == BUFFERED),
-                    .OUTPUT_REG (2 == BUFFERED)
+                    .DATAW    (DATAW),
+                    .PASSTHRU (0 == BUFFERED),
+                    .OUT_REG  (2 == BUFFERED)
                ) out_buffer (
                    .clk       (clk),
                    .reset     (reset),