OUTPUT_REG => OUT_REG renaming

2021-09-09 03:05:38 -07:00
parent a25076b9c1
commit ca46b0a0be
14 changed files with 62 additions and 62 deletions
--- a/hw/rtl/libs/VX_skid_buffer.v
+++ b/hw/rtl/libs/VX_skid_buffer.v
@@ -5,7 +5,7 @@ module VX_skid_buffer #(
    parameter DATAW          = 1,
    parameter PASSTHRU       = 0,
    parameter NOBACKPRESSURE = 0,
-    parameter OUTPUT_REG     = 0
+    parameter OUT_REG     = 0
 ) ( 
    input  wire             clk,
    input  wire             reset,
@@ -51,7 +51,7 @@ module VX_skid_buffer #(
    
    end else begin

-        if (OUTPUT_REG) begin
+        if (OUT_REG) begin

            reg [DATAW-1:0] data_out_r;
            reg [DATAW-1:0] buffer;