OUTPUT_REG => OUT_REG renaming

2021-09-09 03:05:38 -07:00
parent a25076b9c1
commit ca46b0a0be
14 changed files with 62 additions and 62 deletions
--- a/hw/rtl/cache/VX_bank.v
+++ b/hw/rtl/cache/VX_bank.v
@@ -465,9 +465,9 @@ module VX_bank #(
    end

    VX_elastic_buffer #(
-        .DATAW      (NUM_PORTS * (CORE_TAG_WIDTH + 1 + `WORD_WIDTH + `REQS_BITS)),
-        .SIZE       (CRSQ_SIZE),
-        .OUTPUT_REG (1 == NUM_BANKS)
+        .DATAW   (NUM_PORTS * (CORE_TAG_WIDTH + 1 + `WORD_WIDTH + `REQS_BITS)),
+        .SIZE    (CRSQ_SIZE),
+        .OUT_REG (1 == NUM_BANKS)
    ) core_rsp_req (
        .clk       (clk),
        .reset     (reset),