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cache bindings and memory perf refactory

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This commit is contained in:
Blaise Tine
2023-11-03 08:18:18 -04:00
parent 69f9ae778d
commit c9e6518e05
20 changed files with 746 additions and 1025 deletions
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25
hw/rtl/mem/VX_shared_mem.sv
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@@ -13,7 +13,7 @@
`include "VX_define.vh"
module VX_shared_mem #(
module VX_shared_mem import VX_gpu_pkg::*; #(
parameter `STRING INSTANCE_ID = "",
// Size of cache in bytes
@@ -40,7 +40,7 @@ module VX_shared_mem #(
// PERF
`ifdef PERF_ENABLE
VX_cache_perf_if.master cache_perf_if,
output cache_perf_t cache_perf,
`endif
// Core request
@@ -106,6 +106,10 @@ module VX_shared_mem #(
wire [NUM_REQS-1:0][REQ_DATAW-1:0] req_data_in;
wire [NUM_BANKS-1:0][REQ_DATAW-1:0] req_data_out;
`ifdef PERF_ENABLE
wire [`PERF_CTR_BITS-1:0] perf_collisions;
`endif
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign req_data_in[i] = {
req_rw[i],
@@ -125,7 +129,7 @@ module VX_shared_mem #(
.clk (clk),
.reset (reset),
`ifdef PERF_ENABLE
.collisions (cache_perf_if.bank_stalls),
.collisions (perf_collisions),
`else
`UNUSED_PIN (collisions),
`endif
@@ -253,13 +257,14 @@ module VX_shared_mem #(
end
end
assign cache_perf_if.reads = perf_reads;
assign cache_perf_if.writes = perf_writes;
assign cache_perf_if.read_misses = '0;
assign cache_perf_if.write_misses = '0;
assign cache_perf_if.mshr_stalls = '0;
assign cache_perf_if.mem_stalls = '0;
assign cache_perf_if.crsp_stalls = perf_crsp_stalls;
assign cache_perf.reads = perf_reads;
assign cache_perf.writes = perf_writes;
assign cache_perf.read_misses = '0;
assign cache_perf.write_misses = '0;
assign cache_perf.bank_stalls = perf_collisions;
assign cache_perf.mshr_stalls = '0;
assign cache_perf.mem_stalls = '0;
assign cache_perf.crsp_stalls = perf_crsp_stalls;
`endif