lkg build with pipeline + FPU fixes
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@@ -6,15 +6,13 @@
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interface VX_cmt_to_csr_if ();
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wire valid;
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wire [`NW_BITS-1:0] warp_num;
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wire [`NE_BITS:0] num_commits;
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wire upd_fflags;
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wire [`NW_BITS-1:0] fpu_warp_num;
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wire fflags_NV;
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wire fflags_DZ;
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wire fflags_OF;
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wire fflags_UF;
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wire fflags_NX;
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wire [`FFG_BITS-1:0] fflags;
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endinterface
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@@ -5,11 +5,11 @@
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interface VX_csr_io_req_if ();
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wire valid;
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wire [`CSR_ADDR_SIZE-1:0] addr;
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wire rw;
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wire [31:0] data;
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wire ready;
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wire valid;
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wire [`CSR_ADDR_BITS-1:0] addr;
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wire rw;
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wire [31:0] data;
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wire ready;
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endinterface
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@@ -12,7 +12,7 @@ interface VX_csr_req_if ();
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wire [`CSR_BITS-1:0] csr_op;
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wire [`CSR_ADDR_SIZE-1:0] csr_addr;
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wire [`CSR_ADDR_BITS-1:0] csr_addr;
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wire [31:0] csr_mask;
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wire [`NR_BITS-1:0] rd;
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@@ -9,11 +9,7 @@ interface VX_fpu_to_cmt_if ();
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wire [`ISTAG_BITS-1:0] issue_tag;
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wire [`NUM_THREADS-1:0][31:0] data;
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wire upd_fflags;
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wire fflags_NV;
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wire fflags_DZ;
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wire fflags_OF;
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wire fflags_UF;
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wire fflags_NX;
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wire [`NUM_THREADS-1:0][`FFG_BITS-1:0] fflags;
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wire ready;
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endinterface
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