wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

lkg build with pipeline + FPU fixes

Browse Source
This commit is contained in:
Blaise Tine
2020-07-31 09:29:44 -04:00
parent 0d82a8aa4f
commit c9755a0c48
33 changed files with 408 additions and 294 deletions
Download Patch File Download Diff File Expand all files Collapse all files

66
hw/rtl/VX_csr_unit.v
View File

@@ -37,12 +37,11 @@ module VX_csr_unit #(
.select_io_rsp (select_io_rsp)
);
wire [`CSR_ADDR_SIZE-1:0] csr_addr_s2;
wire [31:0] csr_read_data_s2;
wire [31:0] csr_updated_data_s2;
wire [31:0] csr_read_data_unqual;
wire is_csr_s2 = csr_pipe_commit_if.valid;
wire csr_we_s1;
wire [`CSR_ADDR_BITS-1:0] csr_addr_s1;
wire [31:0] csr_read_data, csr_read_data_s1;
wire [31:0] csr_updated_data_s1;
wire [`NW_BITS-1:0] warp_num_s1;
VX_csr_data #(
.CORE_ID(CORE_ID)
@@ -51,51 +50,64 @@ module VX_csr_unit #(
.reset (reset),
.cmt_to_csr_if (cmt_to_csr_if),
.csr_to_fpu_if (csr_to_fpu_if),
.read_enable (csr_pipe_req_if.valid),
.read_addr (csr_pipe_req_if.csr_addr),
.read_data (csr_read_data_unqual),
.write_enable (is_csr_s2),
.write_data (csr_updated_data_s2[`CSR_WIDTH-1:0]),
.write_addr (csr_addr_s2),
.read_data (csr_read_data),
.write_enable (csr_we_s1),
.write_data (csr_updated_data_s1[`CSR_WIDTH-1:0]),
.write_addr (csr_addr_s1),
.warp_num (csr_pipe_req_if.warp_num)
);
);
wire [`NW_BITS-1:0] warp_num_s2;
wire csr_hazard = (csr_addr_s1 == csr_pipe_req_if.csr_addr)
&& (warp_num_s1 == csr_pipe_req_if.warp_num)
&& csr_pipe_commit_if.valid;
wire csr_hazard = (csr_addr_s2 == csr_pipe_req_if.csr_addr)
&& (warp_num_s2 == csr_pipe_req_if.warp_num)
&& is_csr_s2;
wire [31:0] csr_read_data = csr_hazard ? csr_updated_data_s2 : csr_read_data_unqual;
wire [31:0] csr_read_data_qual = csr_hazard ? csr_updated_data_s1 : csr_read_data;
reg [31:0] csr_updated_data;
reg csr_we_s0_unqual;
always @(*) begin
csr_we_s0_unqual = 0;
case (csr_pipe_req_if.csr_op)
`CSR_RW: csr_updated_data = csr_pipe_req_if.csr_mask;
`CSR_RS: csr_updated_data = csr_read_data | csr_pipe_req_if.csr_mask;
`CSR_RC: csr_updated_data = csr_read_data & (32'hFFFFFFFF - csr_pipe_req_if.csr_mask);
`CSR_RW: begin
csr_updated_data = csr_pipe_req_if.csr_mask;
csr_we_s0_unqual = 1;
end
`CSR_RS: begin
csr_updated_data = csr_read_data_qual | csr_pipe_req_if.csr_mask;
csr_we_s0_unqual = (csr_pipe_req_if.csr_mask != 0);
end
`CSR_RC: begin
csr_updated_data = csr_read_data_qual & (32'hFFFFFFFF - csr_pipe_req_if.csr_mask);
csr_we_s0_unqual = (csr_pipe_req_if.csr_mask != 0);
end
default: csr_updated_data = 32'hdeadbeef;
endcase
end
end
wire csr_we_s0 = csr_we_s0_unqual && csr_pipe_req_if.valid;
wire stall = ~csr_pipe_commit_if.ready && csr_pipe_commit_if.valid;
VX_generic_register #(
.N(1 + `ISTAG_BITS + `NW_BITS + `CSR_ADDR_SIZE + 1 + 32 + 32)
.N(1 + `ISTAG_BITS + `NW_BITS + 1 + `CSR_ADDR_BITS + 1 + 32 + 32)
) csr_reg (
.clk (clk),
.reset (reset),
.stall (stall),
.flush (0),
.in ({csr_pipe_req_if.valid, csr_pipe_req_if.issue_tag, csr_pipe_req_if.warp_num, csr_pipe_req_if.csr_addr, csr_pipe_req_if.is_io, csr_read_data, csr_updated_data}),
.out ({csr_pipe_commit_if.valid, csr_pipe_commit_if.issue_tag, warp_num_s2, csr_addr_s2, select_io_rsp, csr_read_data_s2, csr_updated_data_s2})
.in ({csr_pipe_req_if.valid, csr_pipe_req_if.issue_tag, csr_pipe_req_if.warp_num, csr_we_s0, csr_pipe_req_if.csr_addr, csr_pipe_req_if.is_io, csr_read_data_qual, csr_updated_data}),
.out ({csr_pipe_commit_if.valid, csr_pipe_commit_if.issue_tag, warp_num_s1, csr_we_s1, csr_addr_s1, select_io_rsp, csr_read_data_s1, csr_updated_data_s1})
);
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
assign csr_pipe_commit_if.data[i] = (csr_addr_s2 == `CSR_LTID) ? i :
(csr_addr_s2 == `CSR_GTID) ? (csr_read_data_s2 * `NUM_THREADS + i) :
csr_read_data_s2;
assign csr_pipe_commit_if.data[i] = (csr_addr_s1 == `CSR_LTID) ? i :
(csr_addr_s1 == `CSR_GTID) ? (csr_read_data_s1 * `NUM_THREADS + i) :
csr_read_data_s1;
end
assign csr_pipe_req_if.ready = ~stall;