More doc comments

hw/rtl/cache/VX_cache.sv

@@ -250,6 +250,8 @@ module VX_cache #(
     wire [MEM_TAG_IN_WIDTH-1:0]     mem_rsp_tag_c;
     wire                            mem_rsp_ready_c;
 
+    // NOTE(hansung): non-cacheable addresses. Although is this applied for
+    // all address range?
     if (NC_ENABLE) begin
         VX_nc_bypass #( 
             .NUM_PORTS         (NUM_PORTS),

hw/rtl/cache/VX_cache_define.vh

@@ -55,6 +55,7 @@
 
 ///////////////////////////////////////////////////////////////////////////////
 
+// NOTE(hansung): what does CORE_TAG_ID_BITS == 0 mean?
 `define CORE_RSP_TAGS           ((CORE_TAG_ID_BITS != 0) ? 1 : NUM_REQS)
 
 `define LINE_TO_MEM_ADDR(x, i)  {x, `BANK_SELECT_BITS'(i)}