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Parametized cache

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This commit is contained in:
felsabbagh3
2019-10-25 13:36:06 -04:00
parent 89d0390965
commit c85c01e082
6 changed files with 116 additions and 91 deletions
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26
rtl/VX_define.v
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@@ -116,7 +116,31 @@
`define ZERO_REG 5'h0 `define ZERO_REG 5'h0
// Offset
`define CACHE_OFFSET_NB ($clog2(NUM_WORDS_PER_BLOCK))
`define CACHE_OFFSET_ST (2+$clog2(NUMBER_BANKS))
`define CACHE_OFFSET_ED (`CACHE_OFFSET_ST+(`CACHE_OFFSET_NB)-1)
`define CACHE_ADDR_OFFSET_RNG `CACHE_OFFSET_ED:`CACHE_OFFSET_ST
`define CACHE_OFFSET_SIZE_RNG ($clog2(NUM_WORDS_PER_BLOCK)-1):0
// Index
`define NUM_IND (CACHE_SIZE / (CACHE_WAYS * CACHE_BLOCK_PER_BANK))
`define CACHE_IND_NB ($clog2(`NUM_IND))
`define CACHE_IND_ST (`CACHE_OFFSET_ED+1)
`define CACHE_IND_ED (`CACHE_IND_ST+`CACHE_IND_NB-1)
`define CACHE_ADDR_IND_RNG `CACHE_IND_ED:`CACHE_IND_ST
`define CACHE_IND_SIZE_RNG `CACHE_IND_NB-1:0
// Tag
`define CACHE_ADDR_TAG_RNG 31:(`CACHE_IND_ED+1)
`define CACHE_TAG_SIZE_RNG (32-(`CACHE_IND_ED+1)-1):0

9
rtl/VX_dmem_controller.v
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@@ -50,7 +50,14 @@ module VX_dmem_controller (
); );
VX_d_cache dcache( VX_d_cache
#(
.CACHE_SIZE(4096), // Bytes
.CACHE_WAYS(1),
.CACHE_BLOCK(128), // Bytes
.CACHE_BANKS(8)
) dcache
(
.clk (clk), .clk (clk),
.rst (reset), .rst (reset),
.i_p_valid (cache_driver_in_valid), .i_p_valid (cache_driver_in_valid),

50
rtl/cache/VX_Cache_Bank.v vendored
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@@ -2,16 +2,17 @@
// Also add a bit about wheter the "Way ID" is valid / being held or if it is just default // Also add a bit about wheter the "Way ID" is valid / being held or if it is just default
// Also make sure all possible output states are transmitted back to the bank correctly // Also make sure all possible output states are transmitted back to the bank correctly
`define NUM_WORDS_PER_BLOCK 4
`include "../VX_define.v" `include "../VX_define.v"
`include "VX_cache_data.v" `include "VX_cache_data.v"
module VX_Cache_Bank module VX_Cache_Bank
#( #(
// parameter NUMBER_INDEXES = 256 parameter CACHE_SIZE = 4096, // Bytes
parameter NUMBER_INDEXES = 256 parameter CACHE_WAYS = 1,
) parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8
)
( (
clk, clk,
state, state,
@@ -38,9 +39,10 @@ module VX_Cache_Bank
data_evicted data_evicted
); );
parameter cache_entry = 14; localparam NUMBER_BANKS = CACHE_BANKS;
parameter ways_per_set = 4; localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS);
parameter Number_Blocks = 32; localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4);
localparam NUMBER_INDEXES = `NUM_IND;
localparam CACHE_IDLE = 0; // Idle localparam CACHE_IDLE = 0; // Idle
localparam SEND_MEM_REQ = 1; // Write back this block into memory localparam SEND_MEM_REQ = 1; // Write back this block into memory
@@ -52,14 +54,18 @@ module VX_Cache_Bank
//input wire write_from_mem; //input wire write_from_mem;
// Reading Data // Reading Data
input wire[$clog2(NUMBER_INDEXES)-1:0] actual_index; input wire[`CACHE_IND_SIZE_RNG] actual_index;
input wire[16:0] o_tag; // When write_from_mem = 1, o_tag is the new tag
input wire[1:0] block_offset;
input wire[`CACHE_TAG_SIZE_RNG] o_tag; // When write_from_mem = 1, o_tag is the new tag
input wire[`CACHE_OFFSET_SIZE_RNG] block_offset;
input wire[31:0] writedata; input wire[31:0] writedata;
input wire valid_in; input wire valid_in;
input wire read_or_write; // Specifies if it is a read or write operation input wire read_or_write; // Specifies if it is a read or write operation
input wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] fetched_writedata; input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] fetched_writedata;
input wire[2:0] i_p_mem_read; input wire[2:0] i_p_mem_read;
input wire[2:0] i_p_mem_write; input wire[2:0] i_p_mem_write;
input wire[1:0] byte_select; input wire[1:0] byte_select;
@@ -75,11 +81,11 @@ module VX_Cache_Bank
output wire[31:0] eviction_addr; // What's the eviction tag output wire[31:0] eviction_addr; // What's the eviction tag
// Eviction Data (Extraction) // Eviction Data (Extraction)
output wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_evicted; output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_evicted;
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_use; wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use;
wire[16:0] tag_use; wire[16:0] tag_use;
wire[16:0] eviction_tag; wire[16:0] eviction_tag;
wire valid_use; wire valid_use;
@@ -97,7 +103,7 @@ module VX_Cache_Bank
assign eviction_wb = (dirty_use != 1'b0) && valid_use; assign eviction_wb = (dirty_use != 1'b0) && valid_use;
assign eviction_tag = tag_use; assign eviction_tag = tag_use;
assign access = (state == CACHE_IDLE) && valid_in; assign access = (state == CACHE_IDLE) && valid_in;
assign write_from_mem = (state == RECIV_MEM_RSP); assign write_from_mem = (state == RECIV_MEM_RSP) && valid_in; // TODO
assign hit = (access && (tag_use == o_tag) && valid_use); assign hit = (access && (tag_use == o_tag) && valid_use);
//assign eviction_addr = {eviction_tag, actual_index, block_offset, 5'b0}; // Fix with actual data //assign eviction_addr = {eviction_tag, actual_index, block_offset, 5'b0}; // Fix with actual data
assign eviction_addr = {eviction_tag, actual_index, 7'b0}; // Fix with actual data assign eviction_addr = {eviction_tag, actual_index, 7'b0}; // Fix with actual data
@@ -145,10 +151,10 @@ module VX_Cache_Bank
wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100); wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100);
wire[`NUM_WORDS_PER_BLOCK-1:0][3:0] we; wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we;
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_write; wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write;
genvar g; genvar g;
for (g = 0; g < `NUM_WORDS_PER_BLOCK; g = g + 1) begin for (g = 0; g < NUM_WORDS_PER_BLOCK; g = g + 1) begin
wire normal_write = (read_or_write && ((access && (block_offset == g))) && !miss); wire normal_write = (read_or_write && ((access && (block_offset == g))) && !miss);
assign we[g] = (write_from_mem) ? 4'b1111 : assign we[g] = (write_from_mem) ? 4'b1111 :
@@ -162,7 +168,11 @@ module VX_Cache_Bank
assign data_write[g] = write_from_mem ? fetched_writedata[g] : writedata; assign data_write[g] = write_from_mem ? fetched_writedata[g] : writedata;
end end
VX_cache_data data_structures( VX_cache_data #(
.CACHE_SIZE(CACHE_SIZE),
.CACHE_WAYS(CACHE_WAYS),
.CACHE_BLOCK(CACHE_BLOCK),
.CACHE_BANKS(CACHE_BANKS)) data_structures(
.clk (clk), .clk (clk),
// Inputs // Inputs
.addr (actual_index), .addr (actual_index),

46
rtl/cache/VX_cache_data.v vendored
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@@ -1,28 +1,38 @@
`define NUM_WORDS_PER_BLOCK 4
module VX_cache_data ( `include "../VX_define.v"
module VX_cache_data
#(
parameter CACHE_SIZE = 4096, // Bytes
parameter CACHE_WAYS = 1,
parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8
)
(
input wire clk, // Clock input wire clk, // Clock
// Addr // Addr
input wire[$clog2(NUMBER_INDEXES)-1:0] addr, input wire[`CACHE_IND_SIZE_RNG] addr,
// WE // WE
input wire[`NUM_WORDS_PER_BLOCK-1:0][3:0] we, input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we,
input wire evict, input wire evict,
// Data // Data
input wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data
input wire[16:0] tag_write, input wire[`CACHE_TAG_SIZE_RNG] tag_write,
output wire[16:0] tag_use, output wire[`CACHE_TAG_SIZE_RNG] tag_use,
output wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_use, output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
output wire valid_use, output wire valid_use,
output wire dirty_use output wire dirty_use
); );
localparam NUMBER_BANKS = CACHE_BANKS;
parameter NUMBER_INDEXES = 256; localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS);
localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4);
localparam NUMBER_INDEXES = `NUM_IND;
wire currently_writing = (|we); wire currently_writing = (|we);
wire update_dirty = ((!dirty_use) && currently_writing) || (evict); wire update_dirty = ((!dirty_use) && currently_writing) || (evict);
@@ -33,7 +43,7 @@ module VX_cache_data (
`ifndef SYN `ifndef SYN
// (3:0) 4 bytes // (3:0) 4 bytes
reg[`NUM_WORDS_PER_BLOCK-1:0][3:0][7:0] data[NUMBER_INDEXES-1:0]; // Actual Data reg[NUM_WORDS_PER_BLOCK-1:0][3:0][7:0] data[NUMBER_INDEXES-1:0]; // Actual Data
reg[16:0] tag[NUMBER_INDEXES-1:0]; reg[16:0] tag[NUMBER_INDEXES-1:0];
reg valid[NUMBER_INDEXES-1:0]; reg valid[NUMBER_INDEXES-1:0];
reg dirty[NUMBER_INDEXES-1:0]; reg dirty[NUMBER_INDEXES-1:0];
@@ -53,7 +63,7 @@ module VX_cache_data (
end end
always @(posedge clk) begin : data_update always @(posedge clk) begin : data_update
for (f = 0; f < `NUM_WORDS_PER_BLOCK; f = f + 1) begin for (f = 0; f < NUM_WORDS_PER_BLOCK; f = f + 1) begin
if (we[f][0]) data[addr][f][0] <= data_write[f][7 :0 ]; if (we[f][0]) data[addr][f][0] <= data_write[f][7 :0 ];
if (we[f][1]) data[addr][f][1] <= data_write[f][15:8 ]; if (we[f][1]) data[addr][f][1] <= data_write[f][15:8 ];
if (we[f][2]) data[addr][f][2] <= data_write[f][23:16]; if (we[f][2]) data[addr][f][2] <= data_write[f][23:16];
@@ -75,11 +85,11 @@ module VX_cache_data (
wire cena = 1; wire cena = 1;
wire cenb_d = (|we); wire cenb_d = (|we);
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_d = data_write; wire[NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_d = data_write;
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] write_bit_mask_d; wire[NUM_WORDS_PER_BLOCK-1:0][31:0] write_bit_mask_d;
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_d; wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_d;
genvar cur_b; genvar cur_b;
for (cur_b = 0; cur_b < `NUM_WORDS_PER_BLOCK; cur_b=cur_b+1) begin for (cur_b = 0; cur_b < NUM_WORDS_PER_BLOCK; cur_b=cur_b+1) begin
assign write_bit_mask_d[cur_b] = {32{~we[cur_b]}}; assign write_bit_mask_d[cur_b] = {32{~we[cur_b]}};
end end
assign data_use = data_out_d; assign data_use = data_out_d;
@@ -144,8 +154,8 @@ module VX_cache_data (
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_m = {new_tag, new_dirty, new_valid}; wire[NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_m = {new_tag, new_dirty, new_valid};
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_m; wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_m;
assign {old_tag, old_dirty, old_valid} = data_out_m; assign {old_tag, old_dirty, old_valid} = data_out_m;

44
rtl/cache/VX_d_cache.v vendored
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@@ -13,8 +13,15 @@
// `include "VX_Cache_Bank.v" // `include "VX_Cache_Bank.v"
//`include "cache_set.v" //`include "cache_set.v"
module VX_d_cache
module VX_d_cache(clk, #(
parameter CACHE_SIZE = 4096, // Bytes
parameter CACHE_WAYS = 1,
parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8
)
(
clk,
rst, rst,
i_p_addr, i_p_addr,
//i_p_byte_en, //i_p_byte_en,
@@ -39,7 +46,10 @@ module VX_d_cache(clk,
i_m_ready i_m_ready
); );
parameter NUMBER_BANKS = 8; parameter NUMBER_BANKS = CACHE_BANKS;
localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4);
localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / NUMBER_BANKS);
localparam CACHE_IDLE = 0; // Idle localparam CACHE_IDLE = 0; // Idle
localparam SEND_MEM_REQ = 1; // Write back this block into memory localparam SEND_MEM_REQ = 1; // Write back this block into memory
@@ -57,9 +67,9 @@ module VX_d_cache(clk,
output reg [31:0] o_m_evict_addr; // Address is xxxxxxxxxxoooobbbyy output reg [31:0] o_m_evict_addr; // Address is xxxxxxxxxxoooobbbyy
output reg [31:0] o_m_read_addr; output reg [31:0] o_m_read_addr;
output reg o_m_valid; output reg o_m_valid;
output reg[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata; output reg[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
output reg o_m_read_or_write; //, o_m_write; output reg o_m_read_or_write; //, o_m_write;
input wire[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata; input wire[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
input wire i_m_ready; input wire i_m_ready;
input wire[2:0] i_p_mem_read; input wire[2:0] i_p_mem_read;
@@ -118,15 +128,6 @@ module VX_d_cache(clk,
reg[`NT_M1:0] threads_serviced_Qual; reg[`NT_M1:0] threads_serviced_Qual;
// reg detect_bank_conflict;
// genvar bank_ind;
// always @(*) begin
// for (bank_ind = 0; bank_ind < NUMBER_BANKS; bank_ind=bank_ind+1)
// begin
// detect_bank_conflict = detect_bank_conflict | ($countones(thread_track_banks[bank_ind]) > 1);
// end
// end
reg[`NT_M1:0] debug_hit_per_bank_mask[NUMBER_BANKS-1:0]; reg[`NT_M1:0] debug_hit_per_bank_mask[NUMBER_BANKS-1:0];
@@ -229,11 +230,11 @@ module VX_d_cache(clk,
i_p_addr[send_index_to_bank[bank_id]]; i_p_addr[send_index_to_bank[bank_id]];
wire[1:0] byte_select = bank_addr[1:0];
wire[`CACHE_OFFSET_SIZE_RNG] cache_offset = bank_addr[`CACHE_ADDR_OFFSET_RNG];
wire[`CACHE_IND_SIZE_RNG] cache_index = bank_addr[`CACHE_ADDR_IND_RNG];
wire[`CACHE_TAG_SIZE_RNG] cache_tag = bank_addr[`CACHE_ADDR_TAG_RNG];
wire[7:0] cache_index = bank_addr[14:7];
wire[16:0] cache_tag = bank_addr[31:15];
wire[1:0] cache_offset = bank_addr[6:5];
wire[1:0] byte_select = bank_addr[1:0];
wire normal_valid_in = valid_per_bank[bank_id]; wire normal_valid_in = valid_per_bank[bank_id];
wire use_valid_in = ((state == RECIV_MEM_RSP) && i_m_ready) ? 1'b1 : wire use_valid_in = ((state == RECIV_MEM_RSP) && i_m_ready) ? 1'b1 :
@@ -241,7 +242,12 @@ module VX_d_cache(clk,
((state == SEND_MEM_REQ)) ? 1'b0 : ((state == SEND_MEM_REQ)) ? 1'b0 :
normal_valid_in; normal_valid_in;
VX_Cache_Bank bank_structure ( VX_Cache_Bank #(
.CACHE_SIZE(CACHE_SIZE),
.CACHE_WAYS(CACHE_WAYS),
.CACHE_BLOCK(CACHE_BLOCK),
.CACHE_BANKS(CACHE_BANKS)) bank_structure
(
.clk (clk), .clk (clk),
.state (state), .state (state),
.valid_in (use_valid_in), .valid_in (use_valid_in),

32
rtl/simulate/test_bench.h
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@@ -267,38 +267,6 @@ bool Vortex::dbus_driver()
// printf("+++++++ (%x) i_m_readdata[%d][%d] (%d) = %d\n", new_addr, bank_num, offset_num, curr_e, value); // printf("+++++++ (%x) i_m_readdata[%d][%d] (%d) = %d\n", new_addr, bank_num, offset_num, curr_e, value);
} }
// unsigned ordered_mem[32];
// // Create unordered mem
// unsigned unordered_mem[32];
// for (int i = 0; i < CACHE_NUM_BANKS; i++)
// {
// for (int j = 0; j < CACHE_WORDS_PER_BLOCK; j++)
// {
// unordered_mem[(i*CACHE_WORDS_PER_BLOCK)+j] = vortex->o_m_writedata[i][j];
// }
// }
// // Order the memory
// int num_iter = 0;
// for (int i = 0; i < CACHE_NUM_BANKS; i++)
// {
// for (int j = 0; j < (CACHE_NUM_BANKS*CACHE_WORDS_PER_BLOCK); j+=CACHE_WORDS_PER_BLOCK)
// {
// printf("i: %d, j: %d, num_iter: %d\n", i, j, num_iter);
// ordered_mem[i+j] = unordered_mem[num_iter];
// num_iter++;
// }
// }
// // Save the memory
// for (int i = 0; i < (CACHE_WORDS_PER_BLOCK * CACHE_NUM_BANKS); i++)
// {
// unsigned addr = (vortex->o_m_evict_addr) + (4*i);
// unsigned * data_addr = ordered_mem + i;
// ram.writeWord( addr, data_addr);
// }
} }
// Respond next cycle // Respond next cycle