wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

adding data fence support

Browse Source
This commit is contained in:
Blaise Tine
2021-06-28 06:12:18 -07:00
parent 6ae2f5199d
commit c6afc35989
14 changed files with 1044 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
hw/rtl/VX_decode.v
View File

@@ -199,6 +199,10 @@ module VX_decode #(
`USED_REG (rs1_r, 1'b0, rs1);
`USED_REG (rs2_r, 1'b0, rs2);
end
`INST_F: begin
ex_type = `EX_LSU;
op_mod = `MOD_BITS'(0 == func3); // data fence
end
`INST_SYS : begin
if (func3 == 0) begin
ex_type = `EX_ALU;
@@ -241,6 +245,7 @@ module VX_decode #(
`INST_L: begin
ex_type = `EX_LSU;
op_type = `OP_BITS'({1'b0, func3});
op_mod = 0;
use_rd = 1;
imm = {{20{u_12[11]}}, u_12};
`USED_REG (rd_r, (opcode == `INST_FL), rd);
@@ -252,6 +257,7 @@ module VX_decode #(
`INST_S: begin
ex_type = `EX_LSU;
op_type = `OP_BITS'({1'b1, func3});
op_mod = 0;
imm = {{20{func7[6]}}, func7, rd};
`USED_REG (rs1_r, 1'b0, rs1);
`USED_REG (rs2_r, (opcode == `INST_FS), rs2);

1
hw/rtl/VX_define.vh
View File

@@ -152,6 +152,7 @@
`define LSU_FMT(x) x[2:0]
`define LSU_WSIZE(x) x[1:0]
`define LSU_OP(x) x[`LSU_BITS-1:0]
`define LSU_IS_FENCE(x) x[0]
`define CSR_RW 2'h0
`define CSR_RS 2'h1

9
hw/rtl/VX_instr_demux.v
View File

@@ -53,16 +53,17 @@ module VX_instr_demux (
// lsu unit
wire lsu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_LSU);
wire lsu_is_fence = `LSU_IS_FENCE(ibuffer_if.op_mod);
VX_skid_buffer #(
.DATAW (`NW_BITS + `NUM_THREADS + 32 + `LSU_BITS + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32))
.DATAW (`NW_BITS + `NUM_THREADS + 32 + `LSU_BITS + 1 + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32))
) lsu_buffer (
.clk (clk),
.reset (reset),
.valid_in (lsu_req_valid),
.ready_in (lsu_req_ready),
.data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, `LSU_OP(ibuffer_if.op_type), ibuffer_if.imm, ibuffer_if.rd, ibuffer_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}),
.data_out ({lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.op_type, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data}),
.data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, `LSU_OP(ibuffer_if.op_type), lsu_is_fence, ibuffer_if.imm, ibuffer_if.rd, ibuffer_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}),
.data_out ({lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.op_type, lsu_req_if.is_fence, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data}),
.valid_out (lsu_req_if.valid),
.ready_out (lsu_req_if.ready)
);
@@ -88,7 +89,7 @@ module VX_instr_demux (
`ifdef EXT_F_ENABLE
wire fpu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_FPU);
VX_skid_buffer #(
.DATAW (`NW_BITS + `NUM_THREADS + 32 + `FPU_BITS + `MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32))
) fpu_buffer (

20
hw/rtl/VX_lsu_unit.v
View File

@@ -41,6 +41,8 @@ module VX_lsu_unit #(
wire [`NW_BITS-1:0] req_wid;
wire [31:0] req_pc;
wire req_is_dup;
wire mbuf_empty;
wire [`NUM_THREADS-1:0][ADDR_TYPEW-1:0] lsu_addr_type, req_addr_type;
@@ -69,9 +71,14 @@ module VX_lsu_unit #(
assign lsu_addr_type[i] = is_addr_nc;
end
end
// fence stalls the pipeline until all pending requests are sent
wire fence_wait = lsu_req_if.is_fence && (req_valid || !mbuf_empty);
wire ready_in;
wire stall_in = ~ready_in && req_valid;
wire lsu_valid = lsu_req_if.valid && ~fence_wait;
VX_pipe_register #(
.DATAW (1 + 1 + `NW_BITS + `NUM_THREADS + 32 + (`NUM_THREADS * 32) + (`NUM_THREADS * ADDR_TYPEW) + `LSU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32)),
@@ -80,12 +87,12 @@ module VX_lsu_unit #(
.clk (clk),
.reset (reset),
.enable (!stall_in),
.data_in ({lsu_req_if.valid, lsu_is_dup, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, full_addr, lsu_addr_type, lsu_req_if.op_type, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.store_data}),
.data_out ({req_valid, req_is_dup, req_wid, req_tmask, req_pc, req_addr, req_addr_type, req_type, req_rd, req_wb, req_data})
.data_in ({lsu_valid, lsu_is_dup, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, full_addr, lsu_addr_type, lsu_req_if.op_type, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.store_data}),
.data_out ({req_valid, req_is_dup, req_wid, req_tmask, req_pc, req_addr, req_addr_type, req_type, req_rd, req_wb, req_data})
);
// Can accept new request?
assign lsu_req_if.ready = ~stall_in;
assign lsu_req_if.ready = ~stall_in && ~fence_wait;
wire [`NW_BITS-1:0] rsp_wid;
wire [31:0] rsp_pc;
@@ -137,7 +144,7 @@ module VX_lsu_unit #(
.release_addr (mbuf_raddr),
.release_slot (mbuf_pop),
.full (mbuf_full),
`UNUSED_PIN (empty)
.empty (mbuf_empty)
);
wire [`NUM_THREADS-1:0] req_tmask_dup = req_tmask & {{(`NUM_THREADS-1){~req_is_dup}}, 1'b1};
@@ -309,7 +316,10 @@ module VX_lsu_unit #(
end
end
always @(posedge clk) begin
always @(posedge clk) begin
if (lsu_req_if.valid && fence_wait) begin
$display("%t: *** D$%0d fence wait", $time, CORE_ID);
end
if ((| dcache_req_fire)) begin
if (dcache_req_if.rw[0]) begin
$write("%t: D$%0d Wr Req: wid=%0d, PC=%0h, tmask=%b, addr=", $time, CORE_ID, req_wid, req_pc, dcache_req_fire);

1
hw/rtl/interfaces/VX_lsu_req_if.v
View File

@@ -10,6 +10,7 @@ interface VX_lsu_req_if ();
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`LSU_BITS-1:0] op_type;
wire is_fence;
wire [`NUM_THREADS-1:0][31:0] store_data;
wire [`NUM_THREADS-1:0][31:0] base_addr;
wire [31:0] offset;