From c5aec572b5c9cbb662db1ab45296edb0fe03743e Mon Sep 17 00:00:00 2001
From: Blaise Tine <tinebp@yahoo.com>
Date: Thu, 15 Jul 2021 11:46:43 -0700
Subject: [PATCH] minor update

---
 hw/rtl/libs/VX_elastic_buffer.v | 21 ++++++++++++++---
 hw/rtl/libs/VX_onehot_mux.v     | 41 ++++++++++++++++++++++++++++++---
 2 files changed, 56 insertions(+), 6 deletions(-)

diff --git a/hw/rtl/libs/VX_elastic_buffer.v b/hw/rtl/libs/VX_elastic_buffer.v
index c848fa62..a515c836 100644
--- a/hw/rtl/libs/VX_elastic_buffer.v
+++ b/hw/rtl/libs/VX_elastic_buffer.v
@@ -4,8 +4,7 @@ module VX_elastic_buffer #(
     parameter DATAW    = 1,
     parameter SIZE     = 2,
     parameter BUFFERED = 0,
-    parameter FASTRAM  = 0,
-    parameter PASSTHRU = 0
+    parameter FASTRAM  = 0
 ) ( 
     input  wire             clk,
     input  wire             reset,
@@ -18,7 +17,7 @@ module VX_elastic_buffer #(
     input  wire             ready_out,
     output wire             valid_out
 );
-    if (PASSTHRU) begin
+    if (SIZE == 0) begin
 
         `UNUSED_VAR (clk)
         `UNUSED_VAR (reset)
@@ -27,6 +26,22 @@ module VX_elastic_buffer #(
         assign data_out  = data_in;
         assign ready_in  = ready_out;
 
+    end else if (SIZE == 2) begin
+
+        VX_skid_buffer #(
+            .DATAW    (DATAW),
+            .USE_FASTREG (BUFFERED)
+        ) queue (
+            .clk       (clk),
+            .reset     (reset),
+            .valid_in  (valid_in),        
+            .data_in   (data_in),
+            .ready_in  (ready_in),      
+            .valid_out (valid_out),
+            .data_out  (data_out),
+            .ready_out (ready_out)
+        );
+    
     end else begin
         
         wire empty, full;
diff --git a/hw/rtl/libs/VX_onehot_mux.v b/hw/rtl/libs/VX_onehot_mux.v
index 223e5494..a75c7c07 100644
--- a/hw/rtl/libs/VX_onehot_mux.v
+++ b/hw/rtl/libs/VX_onehot_mux.v
@@ -2,15 +2,50 @@
 
 module VX_onehot_mux #(
     parameter DATAW = 1,
-    parameter N     = 1
+    parameter N     = 1,
+    parameter MODEL = 1
 ) (
     input wire [N-1:0][DATAW-1:0] data_in,    
     input wire [N-1:0]            sel_in,    
     output wire [DATAW-1:0]       data_out
 ); 
     if (N > 1) begin
-        for (genvar i = 0; i < N; ++i) begin
-            assign data_out = sel_in[i] ? data_in[i] : 'z;
+        if (MODEL == 1) begin
+            for (genvar i = 0; i < N; ++i) begin
+                assign data_out = sel_in[i] ? data_in[i] : 'z;
+            end
+        end else if (MODEL == 2) begin           
+            reg [DATAW-1:0] data_out_r;
+            always @(*) begin
+                data_out_r = '0;
+                for (integer i = 0; i < N; ++i) begin
+                    data_out_r |= {DATAW{sel_in[i]}} & data_in[i];
+                end
+            end
+            assign data_out = data_out_r; 
+        end else if (MODEL == 3) begin           
+            wire [N-1:0][DATAW-1:0] mask;
+            for (genvar i = 0; i < N; ++i) begin
+                assign mask[i] = {DATAW{sel_in[i]}} & data_in[i];
+            end            
+            for (genvar i = 0; i < DATAW; ++i) begin
+                wire [N-1:0] gather;
+                for (genvar j = 0; j < N; ++j) begin
+                    assign gather[j] = mask[j][i];
+                end
+                assign data_out[i] = (| gather);
+            end       
+        end else begin
+            reg [DATAW-1:0] data_out_r;
+            always @(*) begin
+                data_out_r = 'x;
+                for (integer i = N-1; i >= 0; --i) begin
+                    if (sel_in[i]) begin
+                        data_out_r = data_in[i];
+                    end
+                end
+            end
+            assign data_out = data_out_r; 
         end
     end else begin
         `UNUSED_VAR (sel_in)