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interfaces refactoring

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This commit is contained in:
Blaise Tine
2020-07-02 19:31:55 -07:00
parent ba43e2d33a
commit c5a64a0eed
29 changed files with 295 additions and 297 deletions
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38
hw/rtl/VX_dcache_arb.v
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@@ -21,28 +21,28 @@ module VX_dcache_arb (
// output response
VX_cache_core_rsp_if out_core_rsp_if
);
assign out0_core_req_if.core_req_valid = in_core_req_if.core_req_valid & {`NUM_THREADS{~req_select}};
assign out0_core_req_if.core_req_rw = in_core_req_if.core_req_rw;
assign out0_core_req_if.core_req_byteen = in_core_req_if.core_req_byteen;
assign out0_core_req_if.core_req_addr = in_core_req_if.core_req_addr;
assign out0_core_req_if.core_req_data = in_core_req_if.core_req_data;
assign out0_core_req_if.core_req_tag = in_core_req_if.core_req_tag;
assign out0_core_req_if.valid = in_core_req_if.valid & {`NUM_THREADS{~req_select}};
assign out0_core_req_if.rw = in_core_req_if.rw;
assign out0_core_req_if.byteen = in_core_req_if.byteen;
assign out0_core_req_if.addr = in_core_req_if.addr;
assign out0_core_req_if.data = in_core_req_if.data;
assign out0_core_req_if.tag = in_core_req_if.tag;
assign out1_core_req_if.core_req_valid = in_core_req_if.core_req_valid & {`NUM_THREADS{req_select}};
assign out1_core_req_if.core_req_rw = in_core_req_if.core_req_rw;
assign out1_core_req_if.core_req_byteen = in_core_req_if.core_req_byteen;
assign out1_core_req_if.core_req_addr = in_core_req_if.core_req_addr;
assign out1_core_req_if.core_req_data = in_core_req_if.core_req_data;
assign out1_core_req_if.core_req_tag = in_core_req_if.core_req_tag;
assign out1_core_req_if.valid = in_core_req_if.valid & {`NUM_THREADS{req_select}};
assign out1_core_req_if.rw = in_core_req_if.rw;
assign out1_core_req_if.byteen = in_core_req_if.byteen;
assign out1_core_req_if.addr = in_core_req_if.addr;
assign out1_core_req_if.data = in_core_req_if.data;
assign out1_core_req_if.tag = in_core_req_if.tag;
assign in_core_req_if.core_req_ready = req_select ? out1_core_req_if.core_req_ready : out0_core_req_if.core_req_ready;
assign in_core_req_if.ready = req_select ? out1_core_req_if.ready : out0_core_req_if.ready;
wire rsp_select0 = (| in0_core_rsp_if.core_rsp_valid);
wire rsp_select0 = (| in0_core_rsp_if.valid);
assign out_core_rsp_if.core_rsp_valid = rsp_select0 ? in0_core_rsp_if.core_rsp_valid : in1_core_rsp_if.core_rsp_valid;
assign out_core_rsp_if.core_rsp_data = rsp_select0 ? in0_core_rsp_if.core_rsp_data : in1_core_rsp_if.core_rsp_data;
assign out_core_rsp_if.core_rsp_tag = rsp_select0 ? in0_core_rsp_if.core_rsp_tag : in1_core_rsp_if.core_rsp_tag;
assign in0_core_rsp_if.core_rsp_ready = out_core_rsp_if.core_rsp_ready && rsp_select0;
assign in1_core_rsp_if.core_rsp_ready = out_core_rsp_if.core_rsp_ready && !rsp_select0;
assign out_core_rsp_if.valid = rsp_select0 ? in0_core_rsp_if.valid : in1_core_rsp_if.valid;
assign out_core_rsp_if.data = rsp_select0 ? in0_core_rsp_if.data : in1_core_rsp_if.data;
assign out_core_rsp_if.tag = rsp_select0 ? in0_core_rsp_if.tag : in1_core_rsp_if.tag;
assign in0_core_rsp_if.ready = out_core_rsp_if.ready && rsp_select0;
assign in1_core_rsp_if.ready = out_core_rsp_if.ready && !rsp_select0;
endmodule