From c5a64a0eed9687b291ebf06adeda992679d312ee Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 2 Jul 2020 19:31:55 -0700 Subject: [PATCH] interfaces refactoring --- benchmarks/opencl/vecadd/main.cc | 2 +- driver/rtlsim/Makefile | 2 +- driver/tests/basic/Makefile | 2 +- driver/tests/demo/Makefile | 2 +- hw/rtl/VX_alu_unit.v | 2 +- hw/rtl/VX_core.v | 130 +++++++++++------------ hw/rtl/VX_dcache_arb.v | 38 +++---- hw/rtl/VX_decode.v | 6 +- hw/rtl/VX_exec_unit.v | 25 +++-- hw/rtl/VX_fetch.v | 8 +- hw/rtl/VX_icache_stage.v | 56 +++++----- hw/rtl/VX_lsu_unit.v | 52 ++++----- hw/rtl/VX_mem_unit.v | 130 +++++++++++------------ hw/rtl/VX_pipeline.v | 44 ++++---- hw/rtl/VX_scheduler.v | 1 + hw/rtl/VX_warp_sched.v | 4 +- hw/rtl/interfaces/VX_backend_req_if.v | 8 +- hw/rtl/interfaces/VX_branch_rsp_if.v | 2 +- hw/rtl/interfaces/VX_cache_core_req_if.v | 14 +-- hw/rtl/interfaces/VX_cache_core_rsp_if.v | 8 +- hw/rtl/interfaces/VX_cache_dram_req_if.v | 14 +-- hw/rtl/interfaces/VX_cache_dram_rsp_if.v | 8 +- hw/rtl/interfaces/VX_cache_snp_req_if.v | 10 +- hw/rtl/interfaces/VX_cache_snp_rsp_if.v | 6 +- hw/rtl/interfaces/VX_inst_meta_if.v | 6 +- hw/rtl/interfaces/VX_jal_rsp_if.v | 2 +- hw/rtl/interfaces/VX_join_if.v | 2 +- hw/rtl/pipe_regs/VX_f_d_reg.v | 4 +- hw/rtl/pipe_regs/VX_i_d_reg.v | 4 +- 29 files changed, 295 insertions(+), 297 deletions(-) diff --git a/benchmarks/opencl/vecadd/main.cc b/benchmarks/opencl/vecadd/main.cc index 68c9675a..3b6f889b 100644 --- a/benchmarks/opencl/vecadd/main.cc +++ b/benchmarks/opencl/vecadd/main.cc @@ -4,7 +4,7 @@ #include #include -#define SIZE 4 +#define SIZE 4096 #define NUM_WORK_GROUPS 2 #define KERNEL_NAME "vecadd" diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index 82ab979b..19b39484 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -21,7 +21,7 @@ DBG_FLAGS += -DDBG_CORE_REQ_INFO #CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 #DEBUG=1 -#AFU=1 +AFU=1 CFLAGS += -fPIC diff --git a/driver/tests/basic/Makefile b/driver/tests/basic/Makefile index a3792edc..71e38862 100644 --- a/driver/tests/basic/Makefile +++ b/driver/tests/basic/Makefile @@ -38,7 +38,7 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -L../../stub -lvortex -o $@ run-fpga: $(PROJECT) - LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 256 + LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 4096 run-ase: $(PROJECT) ASE_LOG=0 LD_LIBRARY_PATH=../../opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 256 diff --git a/driver/tests/demo/Makefile b/driver/tests/demo/Makefile index 0368e5b3..bfd6bec0 100644 --- a/driver/tests/demo/Makefile +++ b/driver/tests/demo/Makefile @@ -36,7 +36,7 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -L../../stub -lvortex -o $@ run-fpga: $(PROJECT) - LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 16 + LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 128 run-ase: $(PROJECT) ASE_LOG=0 LD_LIBRARY_PATH=../../opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 16 diff --git a/hw/rtl/VX_alu_unit.v b/hw/rtl/VX_alu_unit.v index 39c1334f..b0d0c20f 100644 --- a/hw/rtl/VX_alu_unit.v +++ b/hw/rtl/VX_alu_unit.v @@ -119,7 +119,7 @@ module VX_alu_unit ( VX_mult #( .WIDTHA(33), .WIDTHB(33), - .WIDTHP(66), + .WIDTHP(64), .SIGNED(1), .PIPELINE(`MUL_LATENCY) ) multiplier ( diff --git a/hw/rtl/VX_core.v b/hw/rtl/VX_core.v index 7d6dc7a1..c437c398 100644 --- a/hw/rtl/VX_core.v +++ b/hw/rtl/VX_core.v @@ -97,18 +97,18 @@ module VX_core #( .DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH) ) dcache_dram_rsp_if(); - assign D_dram_req_valid = dcache_dram_req_if.dram_req_valid; - assign D_dram_req_rw = dcache_dram_req_if.dram_req_rw; - assign D_dram_req_byteen= dcache_dram_req_if.dram_req_byteen; - assign D_dram_req_addr = dcache_dram_req_if.dram_req_addr; - assign D_dram_req_data = dcache_dram_req_if.dram_req_data; - assign D_dram_req_tag = dcache_dram_req_if.dram_req_tag; - assign dcache_dram_req_if.dram_req_ready = D_dram_req_ready; + assign D_dram_req_valid = dcache_dram_req_if.valid; + assign D_dram_req_rw = dcache_dram_req_if.rw; + assign D_dram_req_byteen= dcache_dram_req_if.byteen; + assign D_dram_req_addr = dcache_dram_req_if.addr; + assign D_dram_req_data = dcache_dram_req_if.data; + assign D_dram_req_tag = dcache_dram_req_if.tag; + assign dcache_dram_req_if.ready = D_dram_req_ready; - assign dcache_dram_rsp_if.dram_rsp_valid = D_dram_rsp_valid; - assign dcache_dram_rsp_if.dram_rsp_data = D_dram_rsp_data; - assign dcache_dram_rsp_if.dram_rsp_tag = D_dram_rsp_tag; - assign D_dram_rsp_ready = dcache_dram_rsp_if.dram_rsp_ready; + assign dcache_dram_rsp_if.valid = D_dram_rsp_valid; + assign dcache_dram_rsp_if.data = D_dram_rsp_data; + assign dcache_dram_rsp_if.tag = D_dram_rsp_tag; + assign D_dram_rsp_ready = dcache_dram_rsp_if.ready; VX_cache_core_req_if #( .NUM_REQUESTS(`DNUM_REQUESTS), @@ -124,18 +124,18 @@ module VX_core #( .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) ) core_dcache_rsp_if(), arb_dcache_rsp_if(), arb_io_rsp_if(); - assign io_req_valid = arb_io_req_if.core_req_valid[0]; - assign io_req_rw = arb_io_req_if.core_req_rw[0]; - assign io_req_byteen = arb_io_req_if.core_req_byteen[0]; - assign io_req_addr = arb_io_req_if.core_req_addr[0]; - assign io_req_data = arb_io_req_if.core_req_data[0]; - assign io_req_tag = arb_io_req_if.core_req_tag[0]; - assign arb_io_req_if.core_req_ready = io_req_ready; + assign io_req_valid = arb_io_req_if.valid[0]; + assign io_req_rw = arb_io_req_if.rw[0]; + assign io_req_byteen = arb_io_req_if.byteen[0]; + assign io_req_addr = arb_io_req_if.addr[0]; + assign io_req_data = arb_io_req_if.data[0]; + assign io_req_tag = arb_io_req_if.tag[0]; + assign arb_io_req_if.ready = io_req_ready; - assign arb_io_rsp_if.core_rsp_valid = {{(`NUM_THREADS-1){1'b0}}, io_rsp_valid}; - assign arb_io_rsp_if.core_rsp_data[0] = io_rsp_data; - assign arb_io_rsp_if.core_rsp_tag = io_rsp_tag; - assign io_rsp_ready = arb_io_rsp_if.core_rsp_ready; + assign arb_io_rsp_if.valid = {{(`NUM_THREADS-1){1'b0}}, io_rsp_valid}; + assign arb_io_rsp_if.data[0] = io_rsp_data; + assign arb_io_rsp_if.tag = io_rsp_tag; + assign io_rsp_ready = arb_io_rsp_if.ready; // Icache interfaces @@ -150,18 +150,18 @@ module VX_core #( .DRAM_TAG_WIDTH(`IDRAM_TAG_WIDTH) ) icache_dram_rsp_if(); - assign I_dram_req_valid = icache_dram_req_if.dram_req_valid; - assign I_dram_req_rw = icache_dram_req_if.dram_req_rw; - assign I_dram_req_byteen= icache_dram_req_if.dram_req_byteen; - assign I_dram_req_addr = icache_dram_req_if.dram_req_addr; - assign I_dram_req_data = icache_dram_req_if.dram_req_data; - assign I_dram_req_tag = icache_dram_req_if.dram_req_tag; - assign icache_dram_req_if.dram_req_ready = I_dram_req_ready; + assign I_dram_req_valid = icache_dram_req_if.valid; + assign I_dram_req_rw = icache_dram_req_if.rw; + assign I_dram_req_byteen= icache_dram_req_if.byteen; + assign I_dram_req_addr = icache_dram_req_if.addr; + assign I_dram_req_data = icache_dram_req_if.data; + assign I_dram_req_tag = icache_dram_req_if.tag; + assign icache_dram_req_if.ready = I_dram_req_ready; - assign icache_dram_rsp_if.dram_rsp_valid = I_dram_rsp_valid; - assign icache_dram_rsp_if.dram_rsp_data = I_dram_rsp_data; - assign icache_dram_rsp_if.dram_rsp_tag = I_dram_rsp_tag; - assign I_dram_rsp_ready = icache_dram_rsp_if.dram_rsp_ready; + assign icache_dram_rsp_if.valid = I_dram_rsp_valid; + assign icache_dram_rsp_if.data = I_dram_rsp_data; + assign icache_dram_rsp_if.tag = I_dram_rsp_tag; + assign I_dram_rsp_ready = icache_dram_rsp_if.ready; VX_cache_core_req_if #( .NUM_REQUESTS(`INUM_REQUESTS), @@ -189,34 +189,34 @@ module VX_core #( .reset(reset), // Dcache core request - .dcache_req_valid (core_dcache_req_if.core_req_valid), - .dcache_req_rw (core_dcache_req_if.core_req_rw), - .dcache_req_byteen (core_dcache_req_if.core_req_byteen), - .dcache_req_addr (core_dcache_req_if.core_req_addr), - .dcache_req_data (core_dcache_req_if.core_req_data), - .dcache_req_tag (core_dcache_req_if.core_req_tag), - .dcache_req_ready (core_dcache_req_if.core_req_ready), + .dcache_req_valid (core_dcache_req_if.valid), + .dcache_req_rw (core_dcache_req_if.rw), + .dcache_req_byteen (core_dcache_req_if.byteen), + .dcache_req_addr (core_dcache_req_if.addr), + .dcache_req_data (core_dcache_req_if.data), + .dcache_req_tag (core_dcache_req_if.tag), + .dcache_req_ready (core_dcache_req_if.ready), // Dcache core reponse - .dcache_rsp_valid (core_dcache_rsp_if.core_rsp_valid), - .dcache_rsp_data (core_dcache_rsp_if.core_rsp_data), - .dcache_rsp_tag (core_dcache_rsp_if.core_rsp_tag), - .dcache_rsp_ready (core_dcache_rsp_if.core_rsp_ready), + .dcache_rsp_valid (core_dcache_rsp_if.valid), + .dcache_rsp_data (core_dcache_rsp_if.data), + .dcache_rsp_tag (core_dcache_rsp_if.tag), + .dcache_rsp_ready (core_dcache_rsp_if.ready), // Dcache core request - .icache_req_valid (core_icache_req_if.core_req_valid), - .icache_req_rw (core_icache_req_if.core_req_rw), - .icache_req_byteen (core_icache_req_if.core_req_byteen), - .icache_req_addr (core_icache_req_if.core_req_addr), - .icache_req_data (core_icache_req_if.core_req_data), - .icache_req_tag (core_icache_req_if.core_req_tag), - .icache_req_ready (core_icache_req_if.core_req_ready), + .icache_req_valid (core_icache_req_if.valid), + .icache_req_rw (core_icache_req_if.rw), + .icache_req_byteen (core_icache_req_if.byteen), + .icache_req_addr (core_icache_req_if.addr), + .icache_req_data (core_icache_req_if.data), + .icache_req_tag (core_icache_req_if.tag), + .icache_req_ready (core_icache_req_if.ready), // Dcache core reponse - .icache_rsp_valid (core_icache_rsp_if.core_rsp_valid), - .icache_rsp_data (core_icache_rsp_if.core_rsp_data), - .icache_rsp_tag (core_icache_rsp_if.core_rsp_tag), - .icache_rsp_ready (core_icache_rsp_if.core_rsp_ready), + .icache_rsp_valid (core_icache_rsp_if.valid), + .icache_rsp_data (core_icache_rsp_if.data), + .icache_rsp_tag (core_icache_rsp_if.tag), + .icache_rsp_ready (core_icache_rsp_if.ready), // CSR I/O request .csr_io_req_valid (csr_io_req_valid), @@ -246,15 +246,15 @@ module VX_core #( .SNP_TAG_WIDTH(`DSNP_TAG_WIDTH) ) dcache_snp_rsp_if(); - assign dcache_snp_req_if.snp_req_valid = snp_req_valid; - assign dcache_snp_req_if.snp_req_addr = snp_req_addr; - assign dcache_snp_req_if.snp_req_invalidate = snp_req_invalidate; - assign dcache_snp_req_if.snp_req_tag = snp_req_tag; - assign snp_req_ready = dcache_snp_req_if.snp_req_ready; + assign dcache_snp_req_if.valid = snp_req_valid; + assign dcache_snp_req_if.addr = snp_req_addr; + assign dcache_snp_req_if.invalidate = snp_req_invalidate; + assign dcache_snp_req_if.tag = snp_req_tag; + assign snp_req_ready = dcache_snp_req_if.ready; - assign snp_rsp_valid = dcache_snp_rsp_if.snp_rsp_valid; - assign snp_rsp_tag = dcache_snp_rsp_if.snp_rsp_tag; - assign dcache_snp_rsp_if.snp_rsp_ready = snp_rsp_ready; + assign snp_rsp_valid = dcache_snp_rsp_if.valid; + assign snp_rsp_tag = dcache_snp_rsp_if.tag; + assign dcache_snp_rsp_if.ready = snp_rsp_ready; VX_mem_unit #( .CORE_ID(CORE_ID) @@ -284,8 +284,8 @@ module VX_core #( ); // select io address - wire is_io_addr = ({core_dcache_req_if.core_req_addr[0], 2'b0} >= `IO_BUS_BASE_ADDR); - wire io_select = (| core_dcache_req_if.core_req_valid) ? is_io_addr : 0; + wire is_io_addr = ({core_dcache_req_if.addr[0], 2'b0} >= `IO_BUS_BASE_ADDR); + wire io_select = (| core_dcache_req_if.valid) ? is_io_addr : 0; VX_dcache_arb dcache_io_arb ( .req_select (io_select), diff --git a/hw/rtl/VX_dcache_arb.v b/hw/rtl/VX_dcache_arb.v index 264c91e1..1431be60 100644 --- a/hw/rtl/VX_dcache_arb.v +++ b/hw/rtl/VX_dcache_arb.v @@ -21,28 +21,28 @@ module VX_dcache_arb ( // output response VX_cache_core_rsp_if out_core_rsp_if ); - assign out0_core_req_if.core_req_valid = in_core_req_if.core_req_valid & {`NUM_THREADS{~req_select}}; - assign out0_core_req_if.core_req_rw = in_core_req_if.core_req_rw; - assign out0_core_req_if.core_req_byteen = in_core_req_if.core_req_byteen; - assign out0_core_req_if.core_req_addr = in_core_req_if.core_req_addr; - assign out0_core_req_if.core_req_data = in_core_req_if.core_req_data; - assign out0_core_req_if.core_req_tag = in_core_req_if.core_req_tag; + assign out0_core_req_if.valid = in_core_req_if.valid & {`NUM_THREADS{~req_select}}; + assign out0_core_req_if.rw = in_core_req_if.rw; + assign out0_core_req_if.byteen = in_core_req_if.byteen; + assign out0_core_req_if.addr = in_core_req_if.addr; + assign out0_core_req_if.data = in_core_req_if.data; + assign out0_core_req_if.tag = in_core_req_if.tag; - assign out1_core_req_if.core_req_valid = in_core_req_if.core_req_valid & {`NUM_THREADS{req_select}}; - assign out1_core_req_if.core_req_rw = in_core_req_if.core_req_rw; - assign out1_core_req_if.core_req_byteen = in_core_req_if.core_req_byteen; - assign out1_core_req_if.core_req_addr = in_core_req_if.core_req_addr; - assign out1_core_req_if.core_req_data = in_core_req_if.core_req_data; - assign out1_core_req_if.core_req_tag = in_core_req_if.core_req_tag; + assign out1_core_req_if.valid = in_core_req_if.valid & {`NUM_THREADS{req_select}}; + assign out1_core_req_if.rw = in_core_req_if.rw; + assign out1_core_req_if.byteen = in_core_req_if.byteen; + assign out1_core_req_if.addr = in_core_req_if.addr; + assign out1_core_req_if.data = in_core_req_if.data; + assign out1_core_req_if.tag = in_core_req_if.tag; - assign in_core_req_if.core_req_ready = req_select ? out1_core_req_if.core_req_ready : out0_core_req_if.core_req_ready; + assign in_core_req_if.ready = req_select ? out1_core_req_if.ready : out0_core_req_if.ready; - wire rsp_select0 = (| in0_core_rsp_if.core_rsp_valid); + wire rsp_select0 = (| in0_core_rsp_if.valid); - assign out_core_rsp_if.core_rsp_valid = rsp_select0 ? in0_core_rsp_if.core_rsp_valid : in1_core_rsp_if.core_rsp_valid; - assign out_core_rsp_if.core_rsp_data = rsp_select0 ? in0_core_rsp_if.core_rsp_data : in1_core_rsp_if.core_rsp_data; - assign out_core_rsp_if.core_rsp_tag = rsp_select0 ? in0_core_rsp_if.core_rsp_tag : in1_core_rsp_if.core_rsp_tag; - assign in0_core_rsp_if.core_rsp_ready = out_core_rsp_if.core_rsp_ready && rsp_select0; - assign in1_core_rsp_if.core_rsp_ready = out_core_rsp_if.core_rsp_ready && !rsp_select0; + assign out_core_rsp_if.valid = rsp_select0 ? in0_core_rsp_if.valid : in1_core_rsp_if.valid; + assign out_core_rsp_if.data = rsp_select0 ? in0_core_rsp_if.data : in1_core_rsp_if.data; + assign out_core_rsp_if.tag = rsp_select0 ? in0_core_rsp_if.tag : in1_core_rsp_if.tag; + assign in0_core_rsp_if.ready = out_core_rsp_if.ready && rsp_select0; + assign in1_core_rsp_if.ready = out_core_rsp_if.ready && !rsp_select0; endmodule \ No newline at end of file diff --git a/hw/rtl/VX_decode.v b/hw/rtl/VX_decode.v index 1c001482..dd7e1d1c 100644 --- a/hw/rtl/VX_decode.v +++ b/hw/rtl/VX_decode.v @@ -12,7 +12,7 @@ module VX_decode( ); wire in_valid = (| fd_inst_meta_de.valid); wire[31:0] in_instruction = fd_inst_meta_de.instruction; - wire[31:0] in_curr_PC = fd_inst_meta_de.inst_pc; + wire[31:0] in_curr_PC = fd_inst_meta_de.curr_PC; wire[`NW_BITS-1:0] in_warp_num = fd_inst_meta_de.warp_num; assign frE_to_bckE_req_if.curr_PC = in_curr_PC; @@ -114,8 +114,8 @@ module VX_decode( assign is_split = is_gpgpu && (func3 == 2); // Goes to BE assign is_join = is_gpgpu && (func3 == 3); // Doesn't go to BE - assign join_if.is_join = is_join && in_valid; - assign join_if.join_warp_num = in_warp_num; + assign join_if.is_join = is_join && in_valid; + assign join_if.warp_num = in_warp_num; assign frE_to_bckE_req_if.is_wspawn = is_wspawn; assign frE_to_bckE_req_if.is_tmc = is_tmc; diff --git a/hw/rtl/VX_exec_unit.v b/hw/rtl/VX_exec_unit.v index 51f2da61..d89b4e48 100644 --- a/hw/rtl/VX_exec_unit.v +++ b/hw/rtl/VX_exec_unit.v @@ -61,8 +61,7 @@ module VX_exec_unit ( end endgenerate - wire internal_stall; - assign internal_stall = (| alu_stall); + wire internal_stall = (| alu_stall); assign delay = no_slot_exec || internal_stall; @@ -116,15 +115,15 @@ module VX_exec_unit ( assign inst_exec_wb_if.curr_PC = in_curr_PC; // Jal rsp - assign jal_rsp_temp_if.jal = in_jal; - assign jal_rsp_temp_if.jal_dest = $signed(in_a_reg_data[jal_branch_use_index]) + $signed(in_jal_offset); - assign jal_rsp_temp_if.jal_warp_num = exec_unit_req_if.warp_num; + assign jal_rsp_temp_if.jal = in_jal; + assign jal_rsp_temp_if.jal_dest = $signed(in_a_reg_data[jal_branch_use_index]) + $signed(in_jal_offset); + assign jal_rsp_temp_if.warp_num = exec_unit_req_if.warp_num; // Branch rsp - assign branch_rsp_temp_if.valid_branch = (exec_unit_req_if.branch_type != `BR_NO) && (| exec_unit_req_if.valid); - assign branch_rsp_temp_if.branch_dir = temp_branch_dir; - assign branch_rsp_temp_if.branch_warp_num = exec_unit_req_if.warp_num; - assign branch_rsp_temp_if.branch_dest = $signed(exec_unit_req_if.curr_PC) + ($signed(exec_unit_req_if.itype_immed) << 1); // itype_immed = branch_offset + assign branch_rsp_temp_if.valid_branch = (exec_unit_req_if.branch_type != `BR_NO) && (| exec_unit_req_if.valid); + assign branch_rsp_temp_if.branch_dir = temp_branch_dir; + assign branch_rsp_temp_if.warp_num = exec_unit_req_if.warp_num; + assign branch_rsp_temp_if.branch_dest = $signed(exec_unit_req_if.curr_PC) + ($signed(exec_unit_req_if.itype_immed) << 1); // itype_immed = branch_offset VX_generic_register #( .N(33 + `NW_BITS-1 + 1) @@ -133,8 +132,8 @@ module VX_exec_unit ( .reset (reset), .stall (1'b0), .flush (1'b0), - .in ({jal_rsp_temp_if.jal, jal_rsp_temp_if.jal_dest, jal_rsp_temp_if.jal_warp_num}), - .out ({jal_rsp_if.jal , jal_rsp_if.jal_dest , jal_rsp_if.jal_warp_num}) + .in ({jal_rsp_temp_if.jal, jal_rsp_temp_if.jal_dest, jal_rsp_temp_if.warp_num}), + .out ({jal_rsp_if.jal , jal_rsp_if.jal_dest , jal_rsp_if.warp_num}) ); VX_generic_register #( @@ -144,8 +143,8 @@ module VX_exec_unit ( .reset (reset), .stall (1'b0), .flush (1'b0), - .in ({branch_rsp_temp_if.valid_branch, branch_rsp_temp_if.branch_dir, branch_rsp_temp_if.branch_warp_num, branch_rsp_temp_if.branch_dest}), - .out ({branch_rsp_if.valid_branch , branch_rsp_if.branch_dir , branch_rsp_if.branch_warp_num , branch_rsp_if.branch_dest }) + .in ({branch_rsp_temp_if.valid_branch, branch_rsp_temp_if.branch_dir, branch_rsp_temp_if.warp_num, branch_rsp_temp_if.branch_dest}), + .out ({branch_rsp_if.valid_branch , branch_rsp_if.branch_dir , branch_rsp_if.warp_num , branch_rsp_if.branch_dest }) ); endmodule : VX_exec_unit \ No newline at end of file diff --git a/hw/rtl/VX_fetch.v b/hw/rtl/VX_fetch.v index 1247dac0..e17443f4 100644 --- a/hw/rtl/VX_fetch.v +++ b/hw/rtl/VX_fetch.v @@ -57,7 +57,7 @@ module VX_fetch ( // Join .is_join (join_if.is_join), - .join_warp_num (join_if.join_warp_num), + .join_warp_num (join_if.warp_num), // Split .is_split (warp_ctl_if.is_split), @@ -70,13 +70,13 @@ module VX_fetch ( // JAL .jal (jal_rsp_if.jal), .jal_dest (jal_rsp_if.jal_dest), - .jal_warp_num (jal_rsp_if.jal_warp_num), + .jal_warp_num (jal_rsp_if.warp_num), // Branch .branch_valid (branch_rsp_if.valid_branch), .branch_dir (branch_rsp_if.branch_dir), .branch_dest (branch_rsp_if.branch_dest), - .branch_warp_num (branch_rsp_if.branch_warp_num), + .branch_warp_num (branch_rsp_if.warp_num), // Outputs .thread_mask (thread_mask), @@ -89,7 +89,7 @@ module VX_fetch ( assign fe_inst_meta_fi.warp_num = warp_num; assign fe_inst_meta_fi.valid = thread_mask; assign fe_inst_meta_fi.instruction = 32'h0; - assign fe_inst_meta_fi.inst_pc = warp_pc; + assign fe_inst_meta_fi.curr_PC = warp_pc; `DEBUG_BEGIN wire start_mat_add = scheduled_warp && (warp_pc == 32'h80000ed8) && (warp_num == 0); diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.v index 3985fe05..5232f943 100644 --- a/hw/rtl/VX_icache_stage.v +++ b/hw/rtl/VX_icache_stage.v @@ -25,10 +25,10 @@ module VX_icache_stage #( wire [`LOG2UP(`ICREQ_SIZE)-1:0] mrq_write_addr, mrq_read_addr, dbg_mrq_write_addr; wire mrq_full; - wire mrq_push = icache_req_if.core_req_valid && icache_req_if.core_req_ready; - wire mrq_pop = icache_rsp_if.core_rsp_valid && icache_rsp_if.core_rsp_ready; + wire mrq_push = icache_req_if.valid && icache_req_if.ready; + wire mrq_pop = icache_rsp_if.valid && icache_rsp_if.ready; - assign mrq_read_addr = icache_rsp_if.core_rsp_tag[0][`LOG2UP(`ICREQ_SIZE)-1:0]; + assign mrq_read_addr = icache_rsp_if.tag[0][`LOG2UP(`ICREQ_SIZE)-1:0]; VX_indexable_queue #( .DATAW (`LOG2UP(`ICREQ_SIZE) + 32 + `NW_BITS), @@ -36,13 +36,13 @@ module VX_icache_stage #( ) mem_req_queue ( .clk (clk), .reset (reset), - .write_data ({mrq_write_addr, fe_inst_meta_fi.inst_pc, fe_inst_meta_fi.warp_num}), + .write_data ({mrq_write_addr, fe_inst_meta_fi.curr_PC, fe_inst_meta_fi.warp_num}), .write_addr (mrq_write_addr), .push (mrq_push), .full (mrq_full), .pop (mrq_pop), .read_addr (mrq_read_addr), - .read_data ({dbg_mrq_write_addr, fe_inst_meta_id.inst_pc, fe_inst_meta_id.warp_num}), + .read_data ({dbg_mrq_write_addr, fe_inst_meta_id.curr_PC, fe_inst_meta_id.warp_num}), `UNUSED_PIN (empty) ); @@ -56,48 +56,48 @@ module VX_icache_stage #( end // Icache Request - assign icache_req_if.core_req_valid = valid_inst && !mrq_full; - assign icache_req_if.core_req_rw = 0; - assign icache_req_if.core_req_byteen = 4'b1111; - assign icache_req_if.core_req_addr = fe_inst_meta_fi.inst_pc[31:2]; - assign icache_req_if.core_req_data = 0; + assign icache_req_if.valid = valid_inst && !mrq_full; + assign icache_req_if.rw = 0; + assign icache_req_if.byteen = 4'b1111; + assign icache_req_if.addr = fe_inst_meta_fi.curr_PC[31:2]; + assign icache_req_if.data = 0; // Can't accept new request - assign icache_stage_delay = mrq_full || !icache_req_if.core_req_ready; + assign icache_stage_delay = mrq_full || !icache_req_if.ready; `ifdef DBG_CORE_REQ_INFO - assign icache_req_if.core_req_tag = {fe_inst_meta_fi.inst_pc, 2'b1, 5'b0, fe_inst_meta_fi.warp_num, mrq_write_addr}; + assign icache_req_if.tag = {fe_inst_meta_fi.curr_PC, 2'b1, 5'b0, fe_inst_meta_fi.warp_num, mrq_write_addr}; `else - assign icache_req_if.core_req_tag = mrq_write_addr; + assign icache_req_if.tag = mrq_write_addr; `endif - assign fe_inst_meta_id.instruction = icache_rsp_if.core_rsp_valid ? icache_rsp_if.core_rsp_data[0] : 0; - assign fe_inst_meta_id.valid = icache_rsp_if.core_rsp_valid ? valid_threads[fe_inst_meta_id.warp_num] : 0; + assign fe_inst_meta_id.instruction = icache_rsp_if.valid ? icache_rsp_if.data[0] : 0; + assign fe_inst_meta_id.valid = icache_rsp_if.valid ? valid_threads[fe_inst_meta_id.warp_num] : 0; assign icache_stage_response = mrq_pop; assign icache_stage_wid = fe_inst_meta_id.warp_num; // Can't accept new response - assign icache_rsp_if.core_rsp_ready = !total_freeze; + assign icache_rsp_if.ready = !total_freeze; - `SCOPE_ASSIGN(scope_icache_req_valid, icache_req_if.core_req_valid); + `SCOPE_ASSIGN(scope_icache_req_valid, icache_req_if.valid); `SCOPE_ASSIGN(scope_icache_req_warp_num, fe_inst_meta_fi.warp_num); - `SCOPE_ASSIGN(scope_icache_req_addr, {icache_req_if.core_req_addr, 2'b0}); - `SCOPE_ASSIGN(scope_icache_req_tag, icache_req_if.core_req_tag); - `SCOPE_ASSIGN(scope_icache_req_ready, icache_req_if.core_req_ready); + `SCOPE_ASSIGN(scope_icache_req_addr, {icache_req_if.addr, 2'b0}); + `SCOPE_ASSIGN(scope_icache_req_tag, icache_req_if.tag); + `SCOPE_ASSIGN(scope_icache_req_ready, icache_req_if.ready); - `SCOPE_ASSIGN(scope_icache_rsp_valid, icache_rsp_if.core_rsp_valid); - `SCOPE_ASSIGN(scope_icache_rsp_data, icache_rsp_if.core_rsp_data); - `SCOPE_ASSIGN(scope_icache_rsp_tag, icache_rsp_if.core_rsp_tag); - `SCOPE_ASSIGN(scope_icache_rsp_ready, icache_rsp_if.core_rsp_ready); + `SCOPE_ASSIGN(scope_icache_rsp_valid, icache_rsp_if.valid); + `SCOPE_ASSIGN(scope_icache_rsp_data, icache_rsp_if.data); + `SCOPE_ASSIGN(scope_icache_rsp_tag, icache_rsp_if.tag); + `SCOPE_ASSIGN(scope_icache_rsp_ready, icache_rsp_if.ready); `ifdef DBG_PRINT_CORE_ICACHE always @(posedge clk) begin - if (icache_req_if.core_req_valid && icache_req_if.core_req_ready) begin - $display("%t: I%0d$ req: tag=%0h, pc=%0h, warp=%0d", $time, CORE_ID, mrq_write_addr, fe_inst_meta_fi.inst_pc, fe_inst_meta_fi.warp_num); + if (icache_req_if.valid && icache_req_if.ready) begin + $display("%t: I%0d$ req: tag=%0h, pc=%0h, warp=%0d", $time, CORE_ID, mrq_write_addr, fe_inst_meta_fi.curr_PC, fe_inst_meta_fi.warp_num); end - if (icache_rsp_if.core_rsp_valid && icache_rsp_if.core_rsp_ready) begin - $display("%t: I%0d$ rsp: tag=%0h, pc=%0h, warp=%0d, instr=%0h", $time, CORE_ID, mrq_read_addr, fe_inst_meta_id.inst_pc, fe_inst_meta_id.warp_num, fe_inst_meta_id.instruction); + if (icache_rsp_if.valid && icache_rsp_if.ready) begin + $display("%t: I%0d$ rsp: tag=%0h, pc=%0h, warp=%0d, instr=%0h", $time, CORE_ID, mrq_read_addr, fe_inst_meta_id.curr_PC, fe_inst_meta_id.warp_num, fe_inst_meta_id.instruction); end end `endif diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index 640640b3..4482ab75 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -83,14 +83,14 @@ module VX_lsu_unit #( wire [`LOG2UP(`DCREQ_SIZE)-1:0] mrq_write_addr, mrq_read_addr, dbg_mrq_write_addr; wire mrq_full; - wire mrq_push = (| dcache_req_if.core_req_valid) && dcache_req_if.core_req_ready + wire mrq_push = (| dcache_req_if.valid) && dcache_req_if.ready && (0 == core_req_rw); // only push read requests - wire mrq_pop_part = (| dcache_rsp_if.core_rsp_valid) && dcache_rsp_if.core_rsp_ready; + wire mrq_pop_part = (| dcache_rsp_if.valid) && dcache_rsp_if.ready; - assign mrq_read_addr = dcache_rsp_if.core_rsp_tag[0][`LOG2UP(`DCREQ_SIZE)-1:0]; + assign mrq_read_addr = dcache_rsp_if.tag[0][`LOG2UP(`DCREQ_SIZE)-1:0]; - wire [`NUM_THREADS-1:0] mem_rsp_mask_upd = mem_rsp_mask[mrq_read_addr] & ~dcache_rsp_if.core_rsp_valid; + wire [`NUM_THREADS-1:0] mem_rsp_mask_upd = mem_rsp_mask[mrq_read_addr] & ~dcache_rsp_if.valid; wire mrq_pop = mrq_pop_part && (0 == mem_rsp_mask_upd); @@ -122,20 +122,20 @@ module VX_lsu_unit #( // Core Request - assign dcache_req_if.core_req_valid = use_valid & {`NUM_THREADS{~mrq_full}}; - assign dcache_req_if.core_req_rw = {`NUM_THREADS{core_req_rw}}; - assign dcache_req_if.core_req_byteen= mem_req_byteen; - assign dcache_req_if.core_req_addr = mem_req_addr; - assign dcache_req_if.core_req_data = mem_req_data; + assign dcache_req_if.valid = use_valid & {`NUM_THREADS{~mrq_full}}; + assign dcache_req_if.rw = {`NUM_THREADS{core_req_rw}}; + assign dcache_req_if.byteen= mem_req_byteen; + assign dcache_req_if.addr = mem_req_addr; + assign dcache_req_if.data = mem_req_data; `ifdef DBG_CORE_REQ_INFO - assign dcache_req_if.core_req_tag = {use_pc, use_wb, use_rd, use_warp_num, mrq_write_addr}; + assign dcache_req_if.tag = {use_pc, use_wb, use_rd, use_warp_num, mrq_write_addr}; `else - assign dcache_req_if.core_req_tag = mrq_write_addr; + assign dcache_req_if.tag = mrq_write_addr; `endif // Can't accept new request - assign delay = mrq_full || !dcache_req_if.core_req_ready; + assign delay = mrq_full || !dcache_req_if.ready; // Core Response @@ -143,7 +143,7 @@ module VX_lsu_unit #( wire [`NUM_THREADS-1:0][31:0] rsp_data_shifted; for (i = 0; i < `NUM_THREADS; ++i) begin - assign rsp_data_shifted[i] = (dcache_rsp_if.core_rsp_data[i] >> mem_rsp_offset[i]); + assign rsp_data_shifted[i] = (dcache_rsp_if.data[i] >> mem_rsp_offset[i]); always @(*) begin case (core_rsp_mem_read) `BYTE_EN_SB: core_rsp_data[i] = rsp_data_shifted[i][7] ? (rsp_data_shifted[i] | 32'hFFFFFF00) : (rsp_data_shifted[i] & 32'h000000FF); @@ -155,11 +155,11 @@ module VX_lsu_unit #( end end - assign mem_wb_if.valid = dcache_rsp_if.core_rsp_valid; + assign mem_wb_if.valid = dcache_rsp_if.valid; assign mem_wb_if.data = core_rsp_data; // Can't accept new response - assign dcache_rsp_if.core_rsp_ready = !(no_slot_mem & (|mem_wb_if_p1.valid)); + assign dcache_rsp_if.ready = !(no_slot_mem & (|mem_wb_if_p1.valid)); // From LSU to WB localparam WB_REQ_SIZE = (`NUM_THREADS) + (`NUM_THREADS * 32) + (`NW_BITS) + (5) + (2) + 32; @@ -172,28 +172,28 @@ module VX_lsu_unit #( .out ({mem_wb_if_p1.valid, mem_wb_if_p1.data, mem_wb_if_p1.warp_num, mem_wb_if_p1.rd, mem_wb_if_p1.wb, mem_wb_if_p1.curr_PC}) ); - `SCOPE_ASSIGN(scope_dcache_req_valid, dcache_req_if.core_req_valid); + `SCOPE_ASSIGN(scope_dcache_req_valid, dcache_req_if.valid); `SCOPE_ASSIGN(scope_dcache_req_warp_num, use_warp_num); `SCOPE_ASSIGN(scope_dcache_req_curr_PC, use_pc); `SCOPE_ASSIGN(scope_dcache_req_addr, use_address); `SCOPE_ASSIGN(scope_dcache_req_rw, core_req_rw); - `SCOPE_ASSIGN(scope_dcache_req_byteen,dcache_req_if.core_req_byteen); - `SCOPE_ASSIGN(scope_dcache_req_data, dcache_req_if.core_req_data); - `SCOPE_ASSIGN(scope_dcache_req_tag, dcache_req_if.core_req_tag); - `SCOPE_ASSIGN(scope_dcache_req_ready, dcache_req_if.core_req_ready); + `SCOPE_ASSIGN(scope_dcache_req_byteen,dcache_req_if.byteen); + `SCOPE_ASSIGN(scope_dcache_req_data, dcache_req_if.data); + `SCOPE_ASSIGN(scope_dcache_req_tag, dcache_req_if.tag); + `SCOPE_ASSIGN(scope_dcache_req_ready, dcache_req_if.ready); - `SCOPE_ASSIGN(scope_dcache_rsp_valid, dcache_rsp_if.core_rsp_valid); - `SCOPE_ASSIGN(scope_dcache_rsp_data, dcache_rsp_if.core_rsp_data); - `SCOPE_ASSIGN(scope_dcache_rsp_tag, dcache_rsp_if.core_rsp_tag); - `SCOPE_ASSIGN(scope_dcache_rsp_ready, dcache_rsp_if.core_rsp_ready); + `SCOPE_ASSIGN(scope_dcache_rsp_valid, dcache_rsp_if.valid); + `SCOPE_ASSIGN(scope_dcache_rsp_data, dcache_rsp_if.data); + `SCOPE_ASSIGN(scope_dcache_rsp_tag, dcache_rsp_if.tag); + `SCOPE_ASSIGN(scope_dcache_rsp_ready, dcache_rsp_if.ready); `ifdef DBG_PRINT_CORE_DCACHE always @(posedge clk) begin - if ((| dcache_req_if.core_req_valid) && dcache_req_if.core_req_ready) begin + if ((| dcache_req_if.valid) && dcache_req_if.ready) begin $display("%t: D%0d$ req: valid=%b, addr=%0h, tag=%0h, r=%0d, w=%0d, pc=%0h, rd=%0d, warp=%0d, byteen=%0h, data=%0h", $time, CORE_ID, use_valid, use_address, mrq_write_addr, use_mem_read, use_mem_write, use_pc, use_rd, use_warp_num, mem_req_byteen, mem_req_data); end - if ((| dcache_rsp_if.core_rsp_valid) && dcache_rsp_if.core_rsp_ready) begin + if ((| dcache_rsp_if.valid) && dcache_rsp_if.ready) begin $display("%t: D%0d$ rsp: valid=%b, tag=%0h, pc=%0h, rd=%0d, warp=%0d, data=%0h", $time, CORE_ID, mem_wb_if.valid, mrq_read_addr, mem_wb_if.curr_PC, mem_wb_if.rd, mem_wb_if.warp_num, mem_wb_if.data); end diff --git a/hw/rtl/VX_mem_unit.v b/hw/rtl/VX_mem_unit.v index 6b3c3888..af626723 100644 --- a/hw/rtl/VX_mem_unit.v +++ b/hw/rtl/VX_mem_unit.v @@ -41,8 +41,8 @@ module VX_mem_unit # ( ) core_dcache_rsp_qual_if(), core_smem_rsp_if(); // select shared memory address - wire is_smem_addr = (({core_dcache_req_if.core_req_addr[0], 2'b0} - `SHARED_MEM_BASE_ADDR) <= `SCACHE_SIZE); - wire smem_select = (| core_dcache_req_if.core_req_valid) ? is_smem_addr : 0; + wire is_smem_addr = (({core_dcache_req_if.addr[0], 2'b0} - `SHARED_MEM_BASE_ADDR) <= `SCACHE_SIZE); + wire smem_select = (| core_dcache_req_if.valid) ? is_smem_addr : 0; VX_dcache_arb dcache_smem_arb ( .req_select (smem_select), @@ -84,19 +84,19 @@ module VX_mem_unit # ( .reset (reset), // Core request - .core_req_valid (core_smem_req_if.core_req_valid), - .core_req_rw (core_smem_req_if.core_req_rw), - .core_req_byteen (core_smem_req_if.core_req_byteen), - .core_req_addr (core_smem_req_if.core_req_addr), - .core_req_data (core_smem_req_if.core_req_data), - .core_req_tag (core_smem_req_if.core_req_tag), - .core_req_ready (core_smem_req_if.core_req_ready), + .core_req_valid (core_smem_req_if.valid), + .core_req_rw (core_smem_req_if.rw), + .core_req_byteen (core_smem_req_if.byteen), + .core_req_addr (core_smem_req_if.addr), + .core_req_data (core_smem_req_if.data), + .core_req_tag (core_smem_req_if.tag), + .core_req_ready (core_smem_req_if.ready), // Core response - .core_rsp_valid (core_smem_rsp_if.core_rsp_valid), - .core_rsp_data (core_smem_rsp_if.core_rsp_data), - .core_rsp_tag (core_smem_rsp_if.core_rsp_tag), - .core_rsp_ready (core_smem_rsp_if.core_rsp_ready), + .core_rsp_valid (core_smem_rsp_if.valid), + .core_rsp_data (core_smem_rsp_if.data), + .core_rsp_tag (core_smem_rsp_if.tag), + .core_rsp_ready (core_smem_rsp_if.ready), // DRAM request `UNUSED_PIN (dram_req_valid), @@ -169,46 +169,46 @@ module VX_mem_unit # ( .reset (reset), // Core req - .core_req_valid (core_dcache_req_qual_if.core_req_valid), - .core_req_rw (core_dcache_req_qual_if.core_req_rw), - .core_req_byteen (core_dcache_req_qual_if.core_req_byteen), - .core_req_addr (core_dcache_req_qual_if.core_req_addr), - .core_req_data (core_dcache_req_qual_if.core_req_data), - .core_req_tag (core_dcache_req_qual_if.core_req_tag), - .core_req_ready (core_dcache_req_qual_if.core_req_ready), + .core_req_valid (core_dcache_req_qual_if.valid), + .core_req_rw (core_dcache_req_qual_if.rw), + .core_req_byteen (core_dcache_req_qual_if.byteen), + .core_req_addr (core_dcache_req_qual_if.addr), + .core_req_data (core_dcache_req_qual_if.data), + .core_req_tag (core_dcache_req_qual_if.tag), + .core_req_ready (core_dcache_req_qual_if.ready), // Core response - .core_rsp_valid (core_dcache_rsp_qual_if.core_rsp_valid), - .core_rsp_data (core_dcache_rsp_qual_if.core_rsp_data), - .core_rsp_tag (core_dcache_rsp_qual_if.core_rsp_tag), - .core_rsp_ready (core_dcache_rsp_qual_if.core_rsp_ready), + .core_rsp_valid (core_dcache_rsp_qual_if.valid), + .core_rsp_data (core_dcache_rsp_qual_if.data), + .core_rsp_tag (core_dcache_rsp_qual_if.tag), + .core_rsp_ready (core_dcache_rsp_qual_if.ready), // DRAM request - .dram_req_valid (dcache_dram_req_if.dram_req_valid), - .dram_req_rw (dcache_dram_req_if.dram_req_rw), - .dram_req_byteen (dcache_dram_req_if.dram_req_byteen), - .dram_req_addr (dcache_dram_req_if.dram_req_addr), - .dram_req_data (dcache_dram_req_if.dram_req_data), - .dram_req_tag (dcache_dram_req_if.dram_req_tag), - .dram_req_ready (dcache_dram_req_if.dram_req_ready), + .dram_req_valid (dcache_dram_req_if.valid), + .dram_req_rw (dcache_dram_req_if.rw), + .dram_req_byteen (dcache_dram_req_if.byteen), + .dram_req_addr (dcache_dram_req_if.addr), + .dram_req_data (dcache_dram_req_if.data), + .dram_req_tag (dcache_dram_req_if.tag), + .dram_req_ready (dcache_dram_req_if.ready), // DRAM response - .dram_rsp_valid (dcache_dram_rsp_if.dram_rsp_valid), - .dram_rsp_data (dcache_dram_rsp_if.dram_rsp_data), - .dram_rsp_tag (dcache_dram_rsp_if.dram_rsp_tag), - .dram_rsp_ready (dcache_dram_rsp_if.dram_rsp_ready), + .dram_rsp_valid (dcache_dram_rsp_if.valid), + .dram_rsp_data (dcache_dram_rsp_if.data), + .dram_rsp_tag (dcache_dram_rsp_if.tag), + .dram_rsp_ready (dcache_dram_rsp_if.ready), // Snoop request - .snp_req_valid (dcache_snp_req_if.snp_req_valid), - .snp_req_addr (dcache_snp_req_if.snp_req_addr), - .snp_req_invalidate (dcache_snp_req_if.snp_req_invalidate), - .snp_req_tag (dcache_snp_req_if.snp_req_tag), - .snp_req_ready (dcache_snp_req_if.snp_req_ready), + .snp_req_valid (dcache_snp_req_if.valid), + .snp_req_addr (dcache_snp_req_if.addr), + .snp_req_invalidate (dcache_snp_req_if.invalidate), + .snp_req_tag (dcache_snp_req_if.tag), + .snp_req_ready (dcache_snp_req_if.ready), // Snoop response - .snp_rsp_valid (dcache_snp_rsp_if.snp_rsp_valid), - .snp_rsp_tag (dcache_snp_rsp_if.snp_rsp_tag), - .snp_rsp_ready (dcache_snp_rsp_if.snp_rsp_ready), + .snp_rsp_valid (dcache_snp_rsp_if.valid), + .snp_rsp_tag (dcache_snp_rsp_if.tag), + .snp_rsp_ready (dcache_snp_rsp_if.ready), // Snoop forward out `UNUSED_PIN (snp_fwdout_valid), @@ -253,34 +253,34 @@ module VX_mem_unit # ( .reset (reset), // Core request - .core_req_valid (core_icache_req_if.core_req_valid), - .core_req_rw (core_icache_req_if.core_req_rw), - .core_req_byteen (core_icache_req_if.core_req_byteen), - .core_req_addr (core_icache_req_if.core_req_addr), - .core_req_data (core_icache_req_if.core_req_data), - .core_req_tag (core_icache_req_if.core_req_tag), - .core_req_ready (core_icache_req_if.core_req_ready), + .core_req_valid (core_icache_req_if.valid), + .core_req_rw (core_icache_req_if.rw), + .core_req_byteen (core_icache_req_if.byteen), + .core_req_addr (core_icache_req_if.addr), + .core_req_data (core_icache_req_if.data), + .core_req_tag (core_icache_req_if.tag), + .core_req_ready (core_icache_req_if.ready), // Core response - .core_rsp_valid (core_icache_rsp_if.core_rsp_valid), - .core_rsp_data (core_icache_rsp_if.core_rsp_data), - .core_rsp_tag (core_icache_rsp_if.core_rsp_tag), - .core_rsp_ready (core_icache_rsp_if.core_rsp_ready), + .core_rsp_valid (core_icache_rsp_if.valid), + .core_rsp_data (core_icache_rsp_if.data), + .core_rsp_tag (core_icache_rsp_if.tag), + .core_rsp_ready (core_icache_rsp_if.ready), // DRAM Req - .dram_req_valid (icache_dram_req_if.dram_req_valid), - .dram_req_rw (icache_dram_req_if.dram_req_rw), - .dram_req_byteen (icache_dram_req_if.dram_req_byteen), - .dram_req_addr (icache_dram_req_if.dram_req_addr), - .dram_req_data (icache_dram_req_if.dram_req_data), - .dram_req_tag (icache_dram_req_if.dram_req_tag), - .dram_req_ready (icache_dram_req_if.dram_req_ready), + .dram_req_valid (icache_dram_req_if.valid), + .dram_req_rw (icache_dram_req_if.rw), + .dram_req_byteen (icache_dram_req_if.byteen), + .dram_req_addr (icache_dram_req_if.addr), + .dram_req_data (icache_dram_req_if.data), + .dram_req_tag (icache_dram_req_if.tag), + .dram_req_ready (icache_dram_req_if.ready), // DRAM response - .dram_rsp_valid (icache_dram_rsp_if.dram_rsp_valid), - .dram_rsp_data (icache_dram_rsp_if.dram_rsp_data), - .dram_rsp_tag (icache_dram_rsp_if.dram_rsp_tag), - .dram_rsp_ready (icache_dram_rsp_if.dram_rsp_ready), + .dram_rsp_valid (icache_dram_rsp_if.valid), + .dram_rsp_data (icache_dram_rsp_if.data), + .dram_rsp_tag (icache_dram_rsp_if.tag), + .dram_rsp_ready (icache_dram_rsp_if.ready), // Snoop request .snp_req_valid (0), diff --git a/hw/rtl/VX_pipeline.v b/hw/rtl/VX_pipeline.v index 83833f3d..72c6ee2d 100644 --- a/hw/rtl/VX_pipeline.v +++ b/hw/rtl/VX_pipeline.v @@ -176,31 +176,31 @@ module VX_pipeline #( .ebreak (ebreak) ); - assign dcache_req_valid = core_dcache_req_if.core_req_valid; - assign dcache_req_rw = core_dcache_req_if.core_req_rw; - assign dcache_req_byteen = core_dcache_req_if.core_req_byteen; - assign dcache_req_addr = core_dcache_req_if.core_req_addr; - assign dcache_req_data = core_dcache_req_if.core_req_data; - assign dcache_req_tag = core_dcache_req_if.core_req_tag; - assign core_dcache_req_if.core_req_ready = dcache_req_ready; + assign dcache_req_valid = core_dcache_req_if.valid; + assign dcache_req_rw = core_dcache_req_if.rw; + assign dcache_req_byteen = core_dcache_req_if.byteen; + assign dcache_req_addr = core_dcache_req_if.addr; + assign dcache_req_data = core_dcache_req_if.data; + assign dcache_req_tag = core_dcache_req_if.tag; + assign core_dcache_req_if.ready = dcache_req_ready; - assign core_dcache_rsp_if.core_rsp_valid = dcache_rsp_valid; - assign core_dcache_rsp_if.core_rsp_data = dcache_rsp_data; - assign core_dcache_rsp_if.core_rsp_tag = dcache_rsp_tag; - assign dcache_rsp_ready = core_dcache_rsp_if.core_rsp_ready; + assign core_dcache_rsp_if.valid = dcache_rsp_valid; + assign core_dcache_rsp_if.data = dcache_rsp_data; + assign core_dcache_rsp_if.tag = dcache_rsp_tag; + assign dcache_rsp_ready = core_dcache_rsp_if.ready; - assign icache_req_valid = core_icache_req_if.core_req_valid; - assign icache_req_rw = core_icache_req_if.core_req_rw; - assign icache_req_byteen = core_icache_req_if.core_req_byteen; - assign icache_req_addr = core_icache_req_if.core_req_addr; - assign icache_req_data = core_icache_req_if.core_req_data; - assign icache_req_tag = core_icache_req_if.core_req_tag; - assign core_icache_req_if.core_req_ready = icache_req_ready; + assign icache_req_valid = core_icache_req_if.valid; + assign icache_req_rw = core_icache_req_if.rw; + assign icache_req_byteen = core_icache_req_if.byteen; + assign icache_req_addr = core_icache_req_if.addr; + assign icache_req_data = core_icache_req_if.data; + assign icache_req_tag = core_icache_req_if.tag; + assign core_icache_req_if.ready = icache_req_ready; - assign core_icache_rsp_if.core_rsp_valid = icache_rsp_valid; - assign core_icache_rsp_if.core_rsp_data = icache_rsp_data; - assign core_icache_rsp_if.core_rsp_tag = icache_rsp_tag; - assign icache_rsp_ready = core_icache_rsp_if.core_rsp_ready; + assign core_icache_rsp_if.valid = icache_rsp_valid; + assign core_icache_rsp_if.data = icache_rsp_data; + assign core_icache_rsp_if.tag = icache_rsp_tag; + assign icache_rsp_ready = core_icache_rsp_if.ready; `SCOPE_ASSIGN(scope_busy, busy); `SCOPE_ASSIGN(scope_schedule_delay, schedule_delay); diff --git a/hw/rtl/VX_scheduler.v b/hw/rtl/VX_scheduler.v index fb31cbd9..52810bcc 100644 --- a/hw/rtl/VX_scheduler.v +++ b/hw/rtl/VX_scheduler.v @@ -51,6 +51,7 @@ module VX_scheduler ( integer i, w; wire acquire_rd = (| bckE_req_if.valid) && (bckE_req_if.wb != 0) && (bckE_req_if.rd != 0) && !schedule_delay; + wire release_rd = (| writeback_if.valid) && (writeback_if.wb != 0) && (writeback_if.rd != 0); wire [`NUM_THREADS-1:0] valid_wb_new_mask = rename_table[writeback_if.warp_num][writeback_if.rd] & ~writeback_if.valid; diff --git a/hw/rtl/VX_warp_sched.v b/hw/rtl/VX_warp_sched.v index 6869f3b0..4e0b7aed 100644 --- a/hw/rtl/VX_warp_sched.v +++ b/hw/rtl/VX_warp_sched.v @@ -282,8 +282,6 @@ module VX_warp_sched ( end endgenerate - // wire should_stall = stall || (jal && (warp_to_schedule == jal_warp_num)) || (branch_dir && (warp_to_schedule == branch_warp_num)); - wire should_jal = (jal && (warp_to_schedule == jal_warp_num)); wire should_bra = (branch_valid && branch_dir && (warp_to_schedule == branch_warp_num)); @@ -308,7 +306,7 @@ module VX_warp_sched ( assign use_active = (count_visible_active != 0) ? visible_active : (warp_active & (~warp_stalled) & (~total_barrier_stall) & (~warp_lock)); // Choosing a warp to schedule - VX_rr_arbiter #( + VX_fixed_arbiter #( .N(`NUM_WARPS) ) choose_schedule ( .clk (clk), diff --git a/hw/rtl/interfaces/VX_backend_req_if.v b/hw/rtl/interfaces/VX_backend_req_if.v index 31ab83a8..df0ea5b3 100644 --- a/hw/rtl/interfaces/VX_backend_req_if.v +++ b/hw/rtl/interfaces/VX_backend_req_if.v @@ -5,6 +5,9 @@ interface VX_backend_req_if (); + wire [`NUM_THREADS-1:0] valid; + wire [`NW_BITS-1:0] warp_num; + wire [31:0] curr_PC; wire [11:0] csr_address; wire is_csr; wire csr_immed; @@ -20,14 +23,11 @@ interface VX_backend_req_if (); wire [`BYTE_EN_BITS-1:0] mem_write; wire [2:0] branch_type; wire [19:0] upper_immed; - wire [31:0] curr_PC; wire is_etype; wire is_jal; wire jal; wire [31:0] jal_offset; - wire [31:0] next_PC; - wire [`NUM_THREADS-1:0] valid; - wire [`NW_BITS-1:0] warp_num; + wire [31:0] next_PC; // GPGPU stuff wire is_wspawn; diff --git a/hw/rtl/interfaces/VX_branch_rsp_if.v b/hw/rtl/interfaces/VX_branch_rsp_if.v index 45370ca1..00ac18f1 100644 --- a/hw/rtl/interfaces/VX_branch_rsp_if.v +++ b/hw/rtl/interfaces/VX_branch_rsp_if.v @@ -8,7 +8,7 @@ interface VX_branch_rsp_if (); wire valid_branch; wire branch_dir; wire [31:0] branch_dest; - wire [`NW_BITS-1:0] branch_warp_num; + wire [`NW_BITS-1:0] warp_num; endinterface diff --git a/hw/rtl/interfaces/VX_cache_core_req_if.v b/hw/rtl/interfaces/VX_cache_core_req_if.v index 451418d3..57de39f4 100644 --- a/hw/rtl/interfaces/VX_cache_core_req_if.v +++ b/hw/rtl/interfaces/VX_cache_core_req_if.v @@ -10,13 +10,13 @@ interface VX_cache_core_req_if #( parameter CORE_TAG_ID_BITS = 0 ) (); - wire [NUM_REQUESTS-1:0] core_req_valid; - wire [NUM_REQUESTS-1:0] core_req_rw; - wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] core_req_byteen; - wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr; - wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data; - wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_req_tag; - wire core_req_ready; + wire [NUM_REQUESTS-1:0] valid; + wire [NUM_REQUESTS-1:0] rw; + wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] byteen; + wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] addr; + wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] data; + wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] tag; + wire ready; endinterface diff --git a/hw/rtl/interfaces/VX_cache_core_rsp_if.v b/hw/rtl/interfaces/VX_cache_core_rsp_if.v index 7de31217..5b70f5ee 100644 --- a/hw/rtl/interfaces/VX_cache_core_rsp_if.v +++ b/hw/rtl/interfaces/VX_cache_core_rsp_if.v @@ -10,10 +10,10 @@ interface VX_cache_core_rsp_if #( parameter CORE_TAG_ID_BITS = 0 ) (); - wire [NUM_REQUESTS-1:0] core_rsp_valid; - wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_rsp_data; - wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag; - wire core_rsp_ready; + wire [NUM_REQUESTS-1:0] valid; + wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] data; + wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] tag; + wire ready; endinterface diff --git a/hw/rtl/interfaces/VX_cache_dram_req_if.v b/hw/rtl/interfaces/VX_cache_dram_req_if.v index 5de4fefc..d92b9912 100644 --- a/hw/rtl/interfaces/VX_cache_dram_req_if.v +++ b/hw/rtl/interfaces/VX_cache_dram_req_if.v @@ -9,13 +9,13 @@ interface VX_cache_dram_req_if #( parameter DRAM_TAG_WIDTH = 1 ) (); - wire dram_req_valid; - wire dram_req_rw; - wire [(DRAM_LINE_WIDTH/8)-1:0] dram_req_byteen; - wire [DRAM_ADDR_WIDTH-1:0] dram_req_addr; - wire [DRAM_LINE_WIDTH-1:0] dram_req_data; - wire [DRAM_TAG_WIDTH-1:0] dram_req_tag; - wire dram_req_ready; + wire valid; + wire rw; + wire [(DRAM_LINE_WIDTH/8)-1:0] byteen; + wire [DRAM_ADDR_WIDTH-1:0] addr; + wire [DRAM_LINE_WIDTH-1:0] data; + wire [DRAM_TAG_WIDTH-1:0] tag; + wire ready; endinterface diff --git a/hw/rtl/interfaces/VX_cache_dram_rsp_if.v b/hw/rtl/interfaces/VX_cache_dram_rsp_if.v index ac299c27..9e994d3a 100644 --- a/hw/rtl/interfaces/VX_cache_dram_rsp_if.v +++ b/hw/rtl/interfaces/VX_cache_dram_rsp_if.v @@ -8,10 +8,10 @@ interface VX_cache_dram_rsp_if #( parameter DRAM_TAG_WIDTH = 1 ) (); - wire dram_rsp_valid; - wire [DRAM_LINE_WIDTH-1:0] dram_rsp_data; - wire [DRAM_TAG_WIDTH-1:0] dram_rsp_tag; - wire dram_rsp_ready; + wire valid; + wire [DRAM_LINE_WIDTH-1:0] data; + wire [DRAM_TAG_WIDTH-1:0] tag; + wire ready; endinterface diff --git a/hw/rtl/interfaces/VX_cache_snp_req_if.v b/hw/rtl/interfaces/VX_cache_snp_req_if.v index fce768b8..6134b02d 100644 --- a/hw/rtl/interfaces/VX_cache_snp_req_if.v +++ b/hw/rtl/interfaces/VX_cache_snp_req_if.v @@ -8,11 +8,11 @@ interface VX_cache_snp_req_if #( parameter SNP_TAG_WIDTH = 0 ) (); - wire snp_req_valid; - wire [DRAM_ADDR_WIDTH-1:0] snp_req_addr; - wire snp_req_invalidate; - wire [SNP_TAG_WIDTH-1:0] snp_req_tag; - wire snp_req_ready; + wire valid; + wire [DRAM_ADDR_WIDTH-1:0] addr; + wire invalidate; + wire [SNP_TAG_WIDTH-1:0] tag; + wire ready; endinterface diff --git a/hw/rtl/interfaces/VX_cache_snp_rsp_if.v b/hw/rtl/interfaces/VX_cache_snp_rsp_if.v index 12f6f733..a553c48d 100644 --- a/hw/rtl/interfaces/VX_cache_snp_rsp_if.v +++ b/hw/rtl/interfaces/VX_cache_snp_rsp_if.v @@ -7,9 +7,9 @@ interface VX_cache_snp_rsp_if #( parameter SNP_TAG_WIDTH = 0 ) (); - wire snp_rsp_valid; - wire [SNP_TAG_WIDTH-1:0] snp_rsp_tag; - wire snp_rsp_ready; + wire valid; + wire [SNP_TAG_WIDTH-1:0] tag; + wire ready; endinterface diff --git a/hw/rtl/interfaces/VX_inst_meta_if.v b/hw/rtl/interfaces/VX_inst_meta_if.v index 9cab988f..8ebfa87f 100644 --- a/hw/rtl/interfaces/VX_inst_meta_if.v +++ b/hw/rtl/interfaces/VX_inst_meta_if.v @@ -5,10 +5,10 @@ interface VX_inst_meta_if (); - wire [31:0] instruction; - wire [31:0] inst_pc; - wire [`NW_BITS-1:0] warp_num; wire [`NUM_THREADS-1:0] valid; + wire [31:0] curr_PC; + wire [`NW_BITS-1:0] warp_num; + wire [31:0] instruction; endinterface diff --git a/hw/rtl/interfaces/VX_jal_rsp_if.v b/hw/rtl/interfaces/VX_jal_rsp_if.v index 61e0d73b..c4e2d230 100644 --- a/hw/rtl/interfaces/VX_jal_rsp_if.v +++ b/hw/rtl/interfaces/VX_jal_rsp_if.v @@ -8,7 +8,7 @@ interface VX_jal_rsp_if (); wire jal; wire [31:0] jal_dest; - wire [`NW_BITS-1:0] jal_warp_num; + wire [`NW_BITS-1:0] warp_num; endinterface diff --git a/hw/rtl/interfaces/VX_join_if.v b/hw/rtl/interfaces/VX_join_if.v index 337fc0c0..bc48bfee 100644 --- a/hw/rtl/interfaces/VX_join_if.v +++ b/hw/rtl/interfaces/VX_join_if.v @@ -7,7 +7,7 @@ interface VX_join_if (); wire is_join; - wire [`NW_BITS-1:0] join_warp_num; + wire [`NW_BITS-1:0] warp_num; endinterface diff --git a/hw/rtl/pipe_regs/VX_f_d_reg.v b/hw/rtl/pipe_regs/VX_f_d_reg.v index a2dfba0c..59cf4506 100644 --- a/hw/rtl/pipe_regs/VX_f_d_reg.v +++ b/hw/rtl/pipe_regs/VX_f_d_reg.v @@ -20,8 +20,8 @@ module VX_f_d_reg ( .reset (reset), .stall (stall), .flush (flush), - .in ({fe_inst_meta_fd.instruction, fe_inst_meta_fd.inst_pc, fe_inst_meta_fd.warp_num, fe_inst_meta_fd.valid}), - .out ({fd_inst_meta_de.instruction, fd_inst_meta_de.inst_pc, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid}) + .in ({fe_inst_meta_fd.instruction, fe_inst_meta_fd.curr_PC, fe_inst_meta_fd.warp_num, fe_inst_meta_fd.valid}), + .out ({fd_inst_meta_de.instruction, fd_inst_meta_de.curr_PC, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid}) ); endmodule \ No newline at end of file diff --git a/hw/rtl/pipe_regs/VX_i_d_reg.v b/hw/rtl/pipe_regs/VX_i_d_reg.v index 9963883f..2df17107 100644 --- a/hw/rtl/pipe_regs/VX_i_d_reg.v +++ b/hw/rtl/pipe_regs/VX_i_d_reg.v @@ -20,8 +20,8 @@ module VX_i_d_reg ( .reset (reset), .stall (stall), .flush (flush), - .in ({fe_inst_meta_fd.instruction, fe_inst_meta_fd.inst_pc, fe_inst_meta_fd.warp_num, fe_inst_meta_fd.valid}), - .out ({fd_inst_meta_de.instruction, fd_inst_meta_de.inst_pc, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid}) + .in ({fe_inst_meta_fd.instruction, fe_inst_meta_fd.curr_PC, fe_inst_meta_fd.warp_num, fe_inst_meta_fd.valid}), + .out ({fd_inst_meta_de.instruction, fd_inst_meta_de.curr_PC, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid}) ); endmodule \ No newline at end of file