From c3c9a4b5d831b0c05ab66142c3ebdada3dd0462d Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Tue, 28 Nov 2023 16:05:41 -0800 Subject: [PATCH] [BUGFIX] Fix wrong bitwidth of way_idx when NUM_WAYS=1 When NUM_WAYS=1, CLOG2(NUM_WAYS)-1 becomes -1, setting the MSB of way_idx to a wrong value. --- hw/rtl/cache/VX_cache_data.sv | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/rtl/cache/VX_cache_data.sv b/hw/rtl/cache/VX_cache_data.sv index 493e4884..e0667451 100644 --- a/hw/rtl/cache/VX_cache_data.sv +++ b/hw/rtl/cache/VX_cache_data.sv @@ -93,7 +93,12 @@ module VX_cache_data #( assign wren = fill; end - wire [`CLOG2(NUM_WAYS)-1:0] way_idx; + generate if (NUM_WAYS == 1) begin + wire [0:0] way_idx; + end else begin + wire [`CLOG2(NUM_WAYS)-1:0] way_idx; + end + endgenerate VX_onehot_encoder #( .N (NUM_WAYS)