Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
This commit is contained in:
Blaise Tine
77
hw/unittest/cache/Makefile
vendored
Normal file
77
hw/unittest/cache/Makefile
vendored
Normal file
@@ -0,0 +1,77 @@
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DESTDIR ?= .
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RTL_DIR = ../../rtl
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DPI_DIR = ../../dpi
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CONFIGS +=
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PARAMS +=
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CXXFLAGS += -std=c++11 -Wall -Wextra -Wfatal-errors -Wno-array-bounds
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CXXFLAGS += -fPIC -Wno-maybe-uninitialized
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CXXFLAGS += -I../../.. -I../../common -I../../../../sim/common
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CXXFLAGS += $(CONFIGS)
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LDFLAGS +=
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# control RTL debug tracing states
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DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_BANK
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DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_MSHR
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DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_TAG
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DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_DATA
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DBG_FLAGS += -DDEBUG_LEVEL=$(DEBUG) -DVCD_OUTPUT $(DBG_TRACE_FLAGS)
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RTL_PKGS = $(RTL_DIR)/VX_gpu_pkg.sv
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RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache
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SRCS = cachesim.cpp testbench.cpp
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SRCS += $(DPI_DIR)/util_dpi.cpp
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TOP = VX_cache_top
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VL_FLAGS = --exe
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VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic
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VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO
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VL_FLAGS += --x-initial unique --x-assign unique
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VL_FLAGS += -DSIMULATION
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VL_FLAGS += $(CONFIGS)
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VL_FLAGS += $(PARAMS)
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VL_FLAGS += $(RTL_INCLUDE)
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VL_FLAGS += $(RTL_PKGS)
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VL_FLAGS += --cc $(TOP) --top-module $(TOP)
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# Enable Verilator multithreaded simulation
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THREADS ?= $(shell python -c 'import multiprocessing as mp; print(mp.cpu_count())')
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VL_FLAGS += -j $(THREADS)
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#VL_FLAGS += --threads $(THREADS)
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# Debugigng
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ifdef DEBUG
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VL_FLAGS += --trace --trace-structs $(DBG_FLAGS)
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CXXFLAGS += -g -O0 $(DBG_FLAGS)
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else
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VL_FLAGS += -DNDEBUG
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CXXFLAGS += -O2 -DNDEBUG
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endif
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# Enable perf counters
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ifdef PERF
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VL_FLAGS += -DPERF_ENABLE
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CXXFLAGS += -DPERF_ENABLE
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endif
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PROJECT = cache
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all: $(DESTDIR)/$(PROJECT)
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$(DESTDIR)/$(PROJECT): $(SRCS)
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verilator --build $(VL_FLAGS) $^ -CFLAGS '$(CXXFLAGS)' -o ../$@
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run: $(DESTDIR)/$(PROJECT)
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$(DESTDIR)/$(PROJECT)
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waves: trace.vcd
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gtkwave -o trace.vcd
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clean:
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rm -rf obj_dir $(DESTDIR)/$(PROJECT)
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353
hw/unittest/cache/cachesim.cpp
vendored
Normal file
353
hw/unittest/cache/cachesim.cpp
vendored
Normal file
@@ -0,0 +1,353 @@
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "cachesim.h"
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#include <fstream>
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#include <iomanip>
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#include <iostream>
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#include <vector>
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#include <bitset>
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#ifndef TRACE_START_TIME
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#define TRACE_START_TIME 0ull
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#endif
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#ifndef TRACE_STOP_TIME
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#define TRACE_STOP_TIME -1ull
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#endif
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static uint64_t timestamp = 0;
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static bool trace_enabled = false;
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static uint64_t trace_start_time = TRACE_START_TIME;
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static uint64_t trace_stop_time = TRACE_STOP_TIME;
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double sc_time_stamp() {
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return timestamp;
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}
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bool sim_trace_enabled() {
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if (timestamp >= trace_start_time
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&& timestamp < trace_stop_time)
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return true;
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return trace_enabled;
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}
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void sim_trace_enable(bool enable) {
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trace_enabled = enable;
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}
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CacheSim::CacheSim() {
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// force random values for uninitialized signals
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Verilated::randReset(2);
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ram_ = nullptr;
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cache_ = new VVX_cache_top();
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mem_rsp_active_ = false;
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snp_req_active_ = false;
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#ifdef VCD_OUTPUT
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Verilated::traceEverOn(true);
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trace_ = new VerilatedVcdC;
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cache_->trace(trace_, 99);
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trace_->open("trace.vcd");
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#endif
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}
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CacheSim::~CacheSim() {
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#ifdef VCD_OUTPUT
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trace_->close();
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#endif
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delete cache_;
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//need to delete the req and rsp vectors
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}
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void CacheSim::attach_ram(RAM* ram) {
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ram_ = ram;
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mem_rsp_vec_.clear();
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}
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void CacheSim::reset() {
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#ifndef NDEBUG
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std::cout << timestamp << ": [sim] reset()" << std::endl;
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#endif
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cache_->reset = 1;
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this->step();
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cache_->reset = 0;
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this->step();
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mem_rsp_vec_.clear();
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//clear req and rsp vecs
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}
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void CacheSim::step() {
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//std::cout << timestamp << ": [sim] step()" << std::endl;
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//toggle clock
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cache_->clk = 0;
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this->eval();
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cache_->clk = 1;
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this->eval();
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//handle core and memory reqs and rsps
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this->eval_reqs();
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this->eval_rsps();
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this->eval_mem_bus();
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timestamp++;
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}
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void CacheSim::eval() {
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cache_->eval();
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#ifdef VCD_OUTPUT
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trace_->dump(timestamp);
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#endif
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++timestamp;
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}
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void CacheSim::run(){
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//#ifndef NDEBUG
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//#endif
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this->step();
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int valid = 300;
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int stalls = 20 + 10;
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while (valid > -1) {
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this->step();
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display_miss();
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if(cache_->core_rsp_valid){
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get_core_rsp();
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}
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if(!cache_->core_req_valid && !cache_->core_rsp_valid){
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valid--;
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}
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stalls--;
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if (stalls == 20){
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//stall_mem();
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//send_snoop_req();
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stalls--;
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}
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}
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}
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void CacheSim::clear_req(){
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cache_->core_req_valid = 0;
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}
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void CacheSim::send_req(core_req_t *req){
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core_req_vec_.push(req);
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unsigned int *data = new unsigned int[4];
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core_rsp_vec_.insert(std::pair<unsigned int, unsigned int*>(req->tag, data));
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}
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bool CacheSim::get_core_req_ready(){
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return cache_->core_req_ready;
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}
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bool CacheSim::get_core_rsp_ready(){
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return cache_->core_rsp_ready;
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}
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void CacheSim::eval_reqs(){
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//check to see if cache is accepting reqs
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if(!core_req_vec_.empty() && cache_->core_req_ready){
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core_req_t *req = core_req_vec_.front();
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cache_->core_req_valid = req->valid;
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cache_->core_req_rw = req->rw;
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cache_->core_req_byteen = req->byteen;
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cache_->core_req_addr[0] = req->addr[0];
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cache_->core_req_addr[1] = req->addr[1];
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cache_->core_req_addr[2] = req->addr[2];
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cache_->core_req_addr[3] = req->addr[3];
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cache_->core_req_data[0] = req->data[0];
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cache_->core_req_data[1] = req->data[1];
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cache_->core_req_data[2] = req->data[2];
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cache_->core_req_data[3] = req->data[3];
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cache_->core_req_tag = req->tag;
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core_req_vec_.pop();
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} else {
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clear_req();
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}
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}
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void CacheSim::eval_rsps(){
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//check to see if a request has been responded to
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if (cache_->core_rsp_valid){
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core_rsp_vec_.at(cache_->core_rsp_tag)[0] = cache_->core_rsp_data[0];
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core_rsp_vec_.at(cache_->core_rsp_tag)[1] = cache_->core_rsp_data[1];
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core_rsp_vec_.at(cache_->core_rsp_tag)[2] = cache_->core_rsp_data[2];
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core_rsp_vec_.at(cache_->core_rsp_tag)[3] = cache_->core_rsp_data[3];
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}
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}
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void CacheSim::stall_mem(){
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cache_->mem_req_ready = 0;
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}
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void CacheSim::send_snoop_req(){
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/*cache_->snp_req_valid = 1;
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cache_->snp_req_addr = 0x12222222;
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cache_->snp_req_invalidate = 1;
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cache_->snp_req_tag = 0xff; */
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}
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void CacheSim::eval_mem_bus() {
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if (ram_ == nullptr) {
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cache_->mem_req_ready = 0;
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return;
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}
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// schedule memory responses
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int dequeue_index = -1;
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for (int i = 0; i < mem_rsp_vec_.size(); i++) {
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if (mem_rsp_vec_[i].cycles_left > 0) {
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mem_rsp_vec_[i].cycles_left -= 1;
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}
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if ((dequeue_index == -1)
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&& (mem_rsp_vec_[i].cycles_left == 0)) {
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dequeue_index = i;
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}
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}
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// send memory response
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if (mem_rsp_active_
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&& cache_->mem_rsp_valid
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&& cache_->mem_rsp_ready) {
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mem_rsp_active_ = false;
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}
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if (!mem_rsp_active_) {
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if (dequeue_index != -1) { //time to respond to the request
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cache_->mem_rsp_valid = 1;
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//copy data from the rsp queue to the cache module
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memcpy(cache_->mem_rsp_data.data(), mem_rsp_vec_[dequeue_index].data, MEM_BLOCK_SIZE);
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cache_->mem_rsp_tag = mem_rsp_vec_[dequeue_index].tag;
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free(mem_rsp_vec_[dequeue_index].data); //take data out of the queue
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mem_rsp_vec_.erase(mem_rsp_vec_.begin() + dequeue_index);
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mem_rsp_active_ = true;
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} else {
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cache_->mem_rsp_valid = 0;
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}
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}
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// handle memory stalls
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bool mem_stalled = false;
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#ifdef ENABLE_MEM_STALLS
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if (0 == ((timestamp/2) % MEM_STALLS_MODULO)) {
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mem_stalled = true;
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} else
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if (mem_rsp_vec_.size() >= MEM_RQ_SIZE) {
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mem_stalled = true;
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}
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#endif
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// process memory requests
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if (!mem_stalled) {
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if (cache_->mem_req_valid) {
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if (cache_->mem_req_rw) { //write = 1
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uint64_t byteen = cache_->mem_req_byteen;
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uint64_t base_addr = (cache_->mem_req_addr * MEM_BLOCK_SIZE);
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uint8_t* data = reinterpret_cast<uint8_t*>(cache_->mem_req_data.data());
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for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
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if ((byteen >> i) & 0x1) {
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(*ram_)[base_addr + i] = data[i];
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}
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}
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} else {
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mem_req_t mem_req;
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mem_req.cycles_left = MEM_LATENCY;
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mem_req.data = (uint8_t*)malloc(MEM_BLOCK_SIZE);
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mem_req.tag = cache_->mem_req_tag;
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ram_->read(cache_->mem_req_addr * MEM_BLOCK_SIZE, MEM_BLOCK_SIZE, mem_req.data);
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mem_rsp_vec_.push_back(mem_req);
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}
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}
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}
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cache_->mem_req_ready = ~mem_stalled;
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}
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bool CacheSim::assert_equal(unsigned int* data, unsigned int tag){
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int check = 0;
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unsigned int *rsp = core_rsp_vec_.at(tag);
|
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for (int i = 0; i < 4; ++i){
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for (int j = 0; j < 4; ++j){
|
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if (data[i] == rsp[j]){
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check++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return check;
|
||||
|
||||
}
|
||||
|
||||
//DEBUG
|
||||
|
||||
void CacheSim::display_miss(){
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//int i = (unsigned int)cache_->miss_vec;
|
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//std::bitset<8> x(i);
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//if (i) std::cout << "Miss Vec " << x << std::endl;
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//std::cout << "Miss Vec 0" << cache_->miss_vec[0] << std::endl;
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}
|
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void CacheSim::get_core_req(unsigned int (&rsp)[4]){
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rsp[0] = cache_->core_rsp_data[0];
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rsp[1] = cache_->core_rsp_data[1];
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rsp[2] = cache_->core_rsp_data[2];
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rsp[3] = cache_->core_rsp_data[3];
|
||||
|
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//std::cout << std::hex << "core_rsp_valid: " << cache_->core_rsp_valid << std::endl;
|
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//std::cout << std::hex << "core_rsp_data: " << cache_->core_rsp_data << std::endl;
|
||||
//std::cout << std::hex << "core_rsp_tag: " << cache_->core_rsp_tag << std::endl;
|
||||
}
|
||||
|
||||
void CacheSim::get_core_rsp(){
|
||||
//std::cout << cache_->genblk5_BRA_0_KET_->bank->is_fill_in_pipe<< std::endl;
|
||||
char check = cache_->core_rsp_valid;
|
||||
std::cout << std::hex << "core_rsp_valid: " << (unsigned int) check << std::endl;
|
||||
std::cout << std::hex << "core_rsp_data[0]: " << cache_->core_rsp_data[0] << std::endl;
|
||||
std::cout << std::hex << "core_rsp_data[1]: " << cache_->core_rsp_data[1] << std::endl;
|
||||
std::cout << std::hex << "core_rsp_data[2]: " << cache_->core_rsp_data[2] << std::endl;
|
||||
std::cout << std::hex << "core_rsp_data[3]: " << cache_->core_rsp_data[3] << std::endl;
|
||||
std::cout << std::hex << "core_rsp_tag: " << cache_->core_rsp_tag << std::endl;
|
||||
}
|
||||
|
||||
void CacheSim::get_mem_req(){
|
||||
std::cout << std::hex << "mem_req_valid: " << cache_->mem_req_valid << std::endl;
|
||||
std::cout << std::hex << "mem_req_rw: " << cache_->mem_req_rw << std::endl;
|
||||
std::cout << std::hex << "mem_req_byteen: " << cache_->mem_req_byteen << std::endl;
|
||||
std::cout << std::hex << "mem_req_addr: " << cache_->mem_req_addr << std::endl;
|
||||
std::cout << std::hex << "mem_req_data: " << cache_->mem_req_data << std::endl;
|
||||
std::cout << std::hex << "mem_req_tag: " << cache_->mem_req_tag << std::endl;
|
||||
}
|
||||
|
||||
void CacheSim::get_mem_rsp(){
|
||||
std::cout << std::hex << "mem_rsp_valid: " << cache_->mem_rsp_valid << std::endl;
|
||||
std::cout << std::hex << "mem_rsp_data: " << cache_->mem_rsp_data << std::endl;
|
||||
std::cout << std::hex << "mem_rsp_tag: " << cache_->mem_rsp_tag << std::endl;
|
||||
std::cout << std::hex << "mem_rsp_ready: " << cache_->mem_rsp_ready << std::endl;
|
||||
}
|
||||
105
hw/unittest/cache/cachesim.h
vendored
Normal file
105
hw/unittest/cache/cachesim.h
vendored
Normal file
@@ -0,0 +1,105 @@
|
||||
// Copyright © 2019-2023
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "VVX_cache_top.h"
|
||||
#include "VVX_cache_top__Syms.h"
|
||||
#include "verilated.h"
|
||||
|
||||
#ifdef VCD_OUTPUT
|
||||
#include <verilated_vcd_c.h>
|
||||
#endif
|
||||
|
||||
#include <VX_config.h>
|
||||
#include "ram.h"
|
||||
#include <ostream>
|
||||
#include <vector>
|
||||
#include <queue>
|
||||
|
||||
#define ENABLE_MEM_STALLS
|
||||
#define MEM_LATENCY 100
|
||||
#define MEM_RQ_SIZE 16
|
||||
#define MEM_STALLS_MODULO 16
|
||||
#define MEM_BLOCK_SIZE 16
|
||||
|
||||
typedef struct {
|
||||
int cycles_left;
|
||||
uint8_t *data;
|
||||
unsigned tag;
|
||||
} mem_req_t;
|
||||
|
||||
typedef struct {
|
||||
char valid;
|
||||
char rw;
|
||||
unsigned byteen;
|
||||
unsigned *addr;
|
||||
unsigned *data;
|
||||
unsigned int tag;
|
||||
} core_req_t;
|
||||
|
||||
class CacheSim {
|
||||
public:
|
||||
|
||||
CacheSim();
|
||||
virtual ~CacheSim();
|
||||
|
||||
bool busy();
|
||||
|
||||
void reset();
|
||||
void step();
|
||||
void wait(uint32_t cycles);
|
||||
void attach_ram(RAM* ram);
|
||||
void run(); //run until all reqs are empty
|
||||
|
||||
//req/rsp
|
||||
void send_req(core_req_t *req);
|
||||
void clear_req();
|
||||
void stall_mem();
|
||||
void send_snoop_req();
|
||||
void send_snp_fwd_in();
|
||||
|
||||
//assert funcs
|
||||
bool assert_equal(unsigned int* data, unsigned int tag);
|
||||
|
||||
//debug funcs
|
||||
void get_mem_req();
|
||||
void get_core_req(unsigned int (&rsp)[4]);
|
||||
void get_core_rsp();
|
||||
bool get_core_req_ready();
|
||||
bool get_core_rsp_ready();
|
||||
void get_mem_rsp();
|
||||
void display_miss();
|
||||
|
||||
private:
|
||||
|
||||
void eval();
|
||||
void eval_reqs();
|
||||
void eval_rsps();
|
||||
void eval_mem_bus();
|
||||
|
||||
std::queue<core_req_t*> core_req_vec_;
|
||||
std::vector<mem_req_t> mem_rsp_vec_;
|
||||
std::map<unsigned int, unsigned int*> core_rsp_vec_;
|
||||
int mem_rsp_active_;
|
||||
|
||||
uint32_t snp_req_active_;
|
||||
uint32_t snp_req_size_;
|
||||
uint32_t pending_snp_reqs_;
|
||||
|
||||
VVX_cache_top *cache_;
|
||||
RAM *ram_;
|
||||
#ifdef VCD_OUTPUT
|
||||
VerilatedVcdC *trace_;
|
||||
#endif
|
||||
};
|
||||
77
hw/unittest/cache/ram.h
vendored
Normal file
77
hw/unittest/cache/ram.h
vendored
Normal file
@@ -0,0 +1,77 @@
|
||||
// Copyright © 2019-2023
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
|
||||
class RAM {
|
||||
private:
|
||||
|
||||
mutable uint8_t *mem_[(1 << 12)];
|
||||
|
||||
uint8_t *get(uint32_t address) const {
|
||||
uint32_t block_addr = address >> 20;
|
||||
uint32_t block_offset = address & 0x000FFFFF;
|
||||
if (mem_[block_addr] == NULL) {
|
||||
mem_[block_addr] = new uint8_t[(1 << 20)];
|
||||
}
|
||||
return mem_[block_addr] + block_offset;
|
||||
}
|
||||
|
||||
public:
|
||||
|
||||
RAM() {
|
||||
for (uint32_t i = 0; i < (1 << 12); i++) {
|
||||
mem_[i] = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
~RAM() {
|
||||
this->clear();
|
||||
}
|
||||
|
||||
size_t size() const {
|
||||
return (1ull << 32);
|
||||
}
|
||||
|
||||
void clear() {
|
||||
for (uint32_t i = 0; i < (1 << 12); i++) {
|
||||
if (mem_[i]) {
|
||||
delete [] mem_[i];
|
||||
mem_[i] = NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void read(uint32_t address, uint32_t length, uint8_t *data) const {
|
||||
for (unsigned i = 0; i < length; i++) {
|
||||
data[i] = *this->get(address + i);
|
||||
}
|
||||
}
|
||||
|
||||
void write(uint32_t address, uint32_t length, const uint8_t *data) {
|
||||
for (unsigned i = 0; i < length; i++) {
|
||||
*this->get(address + i) = data[i];
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t& operator[](uint32_t address) {
|
||||
return *get(address);
|
||||
}
|
||||
|
||||
const uint8_t& operator[](uint32_t address) const {
|
||||
return *get(address);
|
||||
}
|
||||
};
|
||||
248
hw/unittest/cache/testbench.cpp
vendored
Normal file
248
hw/unittest/cache/testbench.cpp
vendored
Normal file
@@ -0,0 +1,248 @@
|
||||
// Copyright © 2019-2023
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include "cachesim.h"
|
||||
#include <iostream>
|
||||
#include <fstream>
|
||||
#include <iomanip>
|
||||
|
||||
#define VCD_OUTPUT 1
|
||||
|
||||
|
||||
int REQ_RSP(CacheSim *sim){ //verified
|
||||
unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
|
||||
unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
|
||||
unsigned int rsp[4] = {0,0,0,0};
|
||||
char responded = 0;
|
||||
//write req
|
||||
core_req_t* write = new core_req_t;
|
||||
write->valid = 0xf;
|
||||
write->rw = 0xf;
|
||||
write->byteen = 0xffff;
|
||||
write->addr = addr;
|
||||
write->data = data;
|
||||
write->tag = 0xff;
|
||||
|
||||
//read req
|
||||
core_req_t* read = new core_req_t;
|
||||
read->valid = 0xf;
|
||||
read->rw = 0;
|
||||
read->byteen = 0xffff;
|
||||
read->addr = addr;
|
||||
read->data = addr;
|
||||
read->tag = 0xff;
|
||||
|
||||
// reset the device
|
||||
sim->reset();
|
||||
|
||||
//queue reqs
|
||||
sim->send_req(write);
|
||||
sim->send_req(read);
|
||||
|
||||
sim->run();
|
||||
|
||||
int check = sim->assert_equal(data, write->tag);
|
||||
|
||||
if (check == 4) return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int HIT_1(CacheSim *sim){
|
||||
unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
|
||||
unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
|
||||
unsigned int rsp[4] = {0,0,0,0};
|
||||
char responded = 0;
|
||||
//write req
|
||||
core_req_t* write = new core_req_t;
|
||||
write->valid = 0xf;
|
||||
write->rw = 0xf;
|
||||
write->byteen = 0xffff;
|
||||
write->addr = addr;
|
||||
write->data = data;
|
||||
write->tag = 0x11;
|
||||
|
||||
//read req
|
||||
core_req_t* read = new core_req_t;
|
||||
read->valid = 0xf;
|
||||
read->rw = 0;
|
||||
read->byteen = 0xffff;
|
||||
read->addr = addr;
|
||||
read->data = addr;
|
||||
read->tag = 0x22;
|
||||
|
||||
// reset the device
|
||||
sim->reset();
|
||||
|
||||
//queue reqs
|
||||
sim->send_req(write);
|
||||
sim->send_req(read);
|
||||
|
||||
sim->run();
|
||||
|
||||
bool check = sim->assert_equal(data, write->tag);
|
||||
|
||||
return check;
|
||||
}
|
||||
|
||||
int MISS_1(CacheSim *sim){
|
||||
unsigned int addr1[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
|
||||
unsigned int addr2[4] = {0x12229222, 0xabbbb4bb, 0xcddd47dd, 0xe4423544};
|
||||
unsigned int addr3[4] = {0x12223332, 0xabb454bb, 0xcdddeefd, 0xe4447744};
|
||||
unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
|
||||
unsigned int rsp[4] = {0,0,0,0};
|
||||
char responded = 0;
|
||||
//write req
|
||||
core_req_t* write = new core_req_t;
|
||||
write->valid = 0xf;
|
||||
write->rw = 0xf;
|
||||
write->byteen = 0xffff;
|
||||
write->addr = addr1;
|
||||
write->data = data;
|
||||
write->tag = 0xff;
|
||||
|
||||
//read req
|
||||
core_req_t* read1 = new core_req_t;
|
||||
read1->valid = 0xf;
|
||||
read1->rw = 0;
|
||||
read1->byteen = 0xffff;
|
||||
read1->addr = addr1;
|
||||
read1->data = data;
|
||||
read1->tag = 0xff;
|
||||
|
||||
core_req_t* read2 = new core_req_t;
|
||||
read2->valid = 0xf;
|
||||
read2->rw = 0;
|
||||
read2->byteen = 0xffff;
|
||||
read2->addr = addr2;
|
||||
read2->data = data;
|
||||
read2->tag = 0xff;
|
||||
|
||||
core_req_t* read3 = new core_req_t;
|
||||
read3->valid = 0xf;
|
||||
read3->rw = 0;
|
||||
read3->byteen = 0xffff;
|
||||
read3->addr = addr3;
|
||||
read3->data = data;
|
||||
read3->tag = 0xff;
|
||||
|
||||
// reset the device
|
||||
sim->reset();
|
||||
|
||||
//queue reqs
|
||||
sim->send_req(write);
|
||||
sim->send_req(read1);
|
||||
sim->send_req(read2);
|
||||
sim->send_req(read3);
|
||||
|
||||
sim->run();
|
||||
|
||||
bool check = sim->assert_equal(data, write->tag);
|
||||
|
||||
return check;
|
||||
}
|
||||
int FLUSH(CacheSim *sim){
|
||||
unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
|
||||
unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
|
||||
unsigned int rsp[4] = {0,0,0,0};
|
||||
char responded = 0;
|
||||
//write req
|
||||
core_req_t* write = new core_req_t;
|
||||
write->valid = 0xf;
|
||||
write->rw = 0xf;
|
||||
write->byteen = 0xffff;
|
||||
write->addr = addr;
|
||||
write->data = data;
|
||||
write->tag = 0xff;
|
||||
|
||||
//read req
|
||||
core_req_t* read = new core_req_t;
|
||||
read->valid = 0xf;
|
||||
read->rw = 0;
|
||||
read->byteen = 0xffff;
|
||||
read->addr = addr;
|
||||
read->data = addr;
|
||||
read->tag = 0xff;
|
||||
|
||||
// reset the device
|
||||
sim->reset();
|
||||
|
||||
//queue reqs
|
||||
sim->send_req(write);
|
||||
sim->send_req(read);
|
||||
|
||||
sim->run();
|
||||
|
||||
bool check = sim->assert_equal(data, write->tag);
|
||||
|
||||
return check;
|
||||
}
|
||||
|
||||
|
||||
int BACK_PRESSURE(CacheSim *sim){
|
||||
//happens whenever the core is stalled or memory is stalled
|
||||
unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
|
||||
unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
|
||||
unsigned int rsp[4] = {0,0,0,0};
|
||||
char responded = 0;
|
||||
|
||||
//write req
|
||||
core_req_t* write = new core_req_t;
|
||||
write->valid = 0xf;
|
||||
write->rw = 0xf;
|
||||
write->byteen = 0xffff;
|
||||
write->addr = addr;
|
||||
write->data = data;
|
||||
write->tag = 0xff;
|
||||
|
||||
//read req
|
||||
core_req_t* read = new core_req_t;
|
||||
read->valid = 0xf;
|
||||
read->rw = 0;
|
||||
read->byteen = 0xffff;
|
||||
read->addr = addr;
|
||||
read->data = addr;
|
||||
read->tag = 0xff;
|
||||
|
||||
// reset the device
|
||||
sim->reset();
|
||||
|
||||
//queue reqs
|
||||
for (int i = 0; i < 10; i++){
|
||||
sim->send_req(write);
|
||||
}
|
||||
sim->send_req(read);
|
||||
|
||||
sim->run();
|
||||
|
||||
bool check = sim->assert_equal(data, write->tag);
|
||||
|
||||
return check;
|
||||
}
|
||||
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
//init
|
||||
RAM ram;
|
||||
CacheSim cachesim;
|
||||
cachesim.attach_ram(&ram);
|
||||
int check = REQ_RSP(&cachesim);
|
||||
if(check){
|
||||
std::cout << "PASSED" << std::endl;
|
||||
} else {
|
||||
std::cout << "FAILED" << std::endl;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue
Block a user