Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
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Blaise Tine
257
hw/syn/xilinx/xrt/scripts/package_kernel.tcl
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257
hw/syn/xilinx/xrt/scripts/package_kernel.tcl
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# Copyright © 2019-2023
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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if { $::argc != 4 } {
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puts "ERROR: Program \"$::argv0\" requires 4 arguments!\n"
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puts "Usage: $::argv0 <krnl_name> <vcs_file> <tool_dir> <build_dir>\n"
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exit
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}
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set krnl_name [lindex $::argv 0]
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set vcs_file [lindex $::argv 1]
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set tool_dir [lindex $::argv 2]
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set build_dir [lindex $::argv 3]
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set path_to_packaged "${build_dir}/xo/packaged_kernel"
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set path_to_tmp_project "${build_dir}/xo/project"
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source "${tool_dir}/parse_vcs_list.tcl"
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set vlist [parse_vcs_list "${vcs_file}"]
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set vsources_list [lindex $vlist 0]
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set vincludes_list [lindex $vlist 1]
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set vdefines_list [lindex $vlist 2]
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#puts ${vsources_list}
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#puts ${vincludes_list}
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#puts ${vdefines_list}
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# find if chipscope is enabled
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set chipscope 0
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foreach def $vdefines_list {
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set fields [split $def "="]
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set name [lindex $fields 0]
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if { $name == "CHIPSCOPE" } {
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set chipscope 1
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}
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}
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create_project -force kernel_pack $path_to_tmp_project
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add_files -norecurse ${vsources_list}
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set obj [get_filesets sources_1]
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set files [list \
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[file normalize "${build_dir}/ip/xil_fdiv/xil_fdiv.xci"] \
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[file normalize "${build_dir}/ip/xil_fma/xil_fma.xci"] \
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[file normalize "${build_dir}/ip/xil_fsqrt/xil_fsqrt.xci"] \
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]
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add_files -verbose -norecurse -fileset $obj $files
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set_property include_dirs ${vincludes_list} [current_fileset]
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#set_property verilog_define ${vdefines_list} [current_fileset]
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set obj [get_filesets sources_1]
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set_property -verbose -name "top" -value ${krnl_name} -objects $obj
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if { $chipscope == 1 } {
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# hw debugging
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create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_afu
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set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
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CONFIG.C_EN_STRG_QUAL {1} \
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CONFIG.C_DATA_DEPTH {4096} \
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CONFIG.C_NUM_OF_PROBES {2} \
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CONFIG.C_PROBE0_WIDTH {8} \
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CONFIG.C_PROBE1_WIDTH {24} \
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] [get_ips ila_afu]
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generate_target {instantiation_template} [get_files ila_afu.xci]
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set_property generate_synth_checkpoint false [get_files ila_afu.xci]
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create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_fetch
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set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
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CONFIG.C_EN_STRG_QUAL {1} \
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CONFIG.C_DATA_DEPTH {4096} \
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CONFIG.C_NUM_OF_PROBES {3} \
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CONFIG.C_PROBE0_WIDTH {128} \
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CONFIG.C_PROBE1_WIDTH {128} \
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CONFIG.C_PROBE2_WIDTH {128} \
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] [get_ips ila_fetch]
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generate_target {instantiation_template} [get_files ila_fetch.xci]
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set_property generate_synth_checkpoint false [get_files ila_fetch.xci]
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create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_issue
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set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
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CONFIG.C_EN_STRG_QUAL {1} \
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CONFIG.C_DATA_DEPTH {4096} \
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CONFIG.C_NUM_OF_PROBES {2} \
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CONFIG.C_PROBE0_WIDTH {256} \
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CONFIG.C_PROBE1_WIDTH {128} \
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] [get_ips ila_issue]
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generate_target {instantiation_template} [get_files ila_issue.xci]
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set_property generate_synth_checkpoint false [get_files ila_issue.xci]
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create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_lsu
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set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
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CONFIG.C_EN_STRG_QUAL {1} \
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CONFIG.C_DATA_DEPTH {4096} \
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CONFIG.C_NUM_OF_PROBES {4} \
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CONFIG.C_PROBE0_WIDTH {256} \
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CONFIG.C_PROBE1_WIDTH {128} \
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CONFIG.C_PROBE2_WIDTH {288} \
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CONFIG.C_PROBE3_WIDTH {256} \
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] [get_ips ila_lsu]
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generate_target {instantiation_template} [get_files ila_lsu.xci]
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set_property generate_synth_checkpoint false [get_files ila_lsu.xci]
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create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_msched
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set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
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CONFIG.C_EN_STRG_QUAL {1} \
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CONFIG.C_DATA_DEPTH {4096} \
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CONFIG.C_NUM_OF_PROBES {4} \
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CONFIG.C_PROBE0_WIDTH {128} \
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CONFIG.C_PROBE1_WIDTH {128} \
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CONFIG.C_PROBE2_WIDTH {128} \
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CONFIG.C_PROBE3_WIDTH {128} \
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] [get_ips ila_msched]
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generate_target {instantiation_template} [get_files ila_msched.xci]
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set_property generate_synth_checkpoint false [get_files ila_msched.xci]
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}
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update_compile_order -fileset sources_1
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update_compile_order -fileset sim_1
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ipx::package_project -root_dir $path_to_packaged -vendor xilinx.com -library RTLKernel -taxonomy /KernelIP -import_files -set_current false
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ipx::unload_core $path_to_packaged/component.xml
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ipx::edit_ip_in_project -upgrade true -name tmp_edit_project -directory $path_to_packaged $path_to_packaged/component.xml
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set core [ipx::current_core]
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set_property core_revision 2 $core
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foreach up [ipx::get_user_parameters] {
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ipx::remove_user_parameter [get_property NAME $up] $core
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}
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ipx::associate_bus_interfaces -busif s_axi_ctrl -clock ap_clk $core
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for {set i 0} {$i < 1} {incr i} {
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ipx::associate_bus_interfaces -busif m_axi_mem_$i -clock ap_clk $core
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}
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set mem_map [::ipx::add_memory_map -quiet "s_axi_ctrl" $core]
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set addr_block [::ipx::add_address_block -quiet "reg0" $mem_map]
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set reg [::ipx::add_register "CTRL" $addr_block]
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set_property description "Control signals" $reg
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set_property address_offset 0x000 $reg
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set_property size 32 $reg
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set field [ipx::add_field AP_START $reg]
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set_property ACCESS {read-write} $field
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set_property BIT_OFFSET {0} $field
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set_property BIT_WIDTH {1} $field
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set_property DESCRIPTION {Control signal Register for 'ap_start'.} $field
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set_property MODIFIED_WRITE_VALUE {modify} $field
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set field [ipx::add_field AP_DONE $reg]
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set_property ACCESS {read-only} $field
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set_property BIT_OFFSET {1} $field
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set_property BIT_WIDTH {1} $field
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set_property DESCRIPTION {Control signal Register for 'ap_done'.} $field
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set_property READ_ACTION {modify} $field
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set field [ipx::add_field AP_IDLE $reg]
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set_property ACCESS {read-only} $field
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set_property BIT_OFFSET {2} $field
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set_property BIT_WIDTH {1} $field
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set_property DESCRIPTION {Control signal Register for 'ap_idle'.} $field
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set_property READ_ACTION {modify} $field
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set field [ipx::add_field AP_READY $reg]
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set_property ACCESS {read-only} $field
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set_property BIT_OFFSET {3} $field
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set_property BIT_WIDTH {1} $field
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set_property DESCRIPTION {Control signal Register for 'ap_ready'.} $field
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set_property READ_ACTION {modify} $field
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set field [ipx::add_field RESERVED_1 $reg]
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set_property ACCESS {read-only} $field
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set_property BIT_OFFSET {4} $field
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set_property BIT_WIDTH {3} $field
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set_property DESCRIPTION {Reserved. 0s on read.} $field
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set_property READ_ACTION {modify} $field
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set field [ipx::add_field AUTO_RESTART $reg]
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set_property ACCESS {read-write} $field
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set_property BIT_OFFSET {7} $field
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set_property BIT_WIDTH {1} $field
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set_property DESCRIPTION {Control signal Register for 'auto_restart'.} $field
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set_property MODIFIED_WRITE_VALUE {modify} $field
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set field [ipx::add_field RESERVED_2 $reg]
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set_property ACCESS {read-only} $field
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set_property BIT_OFFSET {8} $field
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set_property BIT_WIDTH {24} $field
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set_property DESCRIPTION {Reserved. 0s on read.} $field
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set_property READ_ACTION {modify} $field
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set reg [::ipx::add_register "GIER" $addr_block]
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set_property description "Global Interrupt Enable Register" $reg
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set_property address_offset 0x004 $reg
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set_property size 32 $reg
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set reg [::ipx::add_register "IP_IER" $addr_block]
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set_property description "IP Interrupt Enable Register" $reg
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set_property address_offset 0x008 $reg
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set_property size 32 $reg
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set reg [::ipx::add_register "IP_ISR" $addr_block]
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set_property description "IP Interrupt Status Register" $reg
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set_property address_offset 0x00C $reg
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set_property size 32 $reg
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set reg [::ipx::add_register -quiet "DEV" $addr_block]
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set_property address_offset 0x010 $reg
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set_property size [expr {8*8}] $reg
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set reg [::ipx::add_register -quiet "ISA" $addr_block]
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set_property address_offset 0x01C $reg
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set_property size [expr {8*8}] $reg
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set reg [::ipx::add_register -quiet "DCR" $addr_block]
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set_property address_offset 0x028 $reg
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set_property size [expr {8*8}] $reg
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set reg [::ipx::add_register -quiet "SCP" $addr_block]
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set_property address_offset 0x034 $reg
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set_property size [expr {8*8}] $reg
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for {set i 0} {$i < 1} {incr i} {
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set reg [::ipx::add_register -quiet "MEM_$i" $addr_block]
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set_property address_offset [expr {0x040 + $i * 12}] $reg
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set_property size [expr {8*8}] $reg
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set regparam [::ipx::add_register_parameter -quiet {ASSOCIATED_BUSIF} $reg]
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set_property value m_axi_mem_$i $regparam
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}
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set_property slave_memory_map_ref "s_axi_ctrl" [::ipx::get_bus_interfaces -of $core "s_axi_ctrl"]
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set_property xpm_libraries {XPM_CDC XPM_MEMORY XPM_FIFO} $core
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set_property sdx_kernel true $core
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set_property sdx_kernel_type rtl $core
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set_property supported_families { } $core
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set_property auto_family_support_level level_2 $core
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ipx::create_xgui_files $core
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ipx::update_checksums $core
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ipx::check_integrity -kernel $core
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ipx::save_core $core
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close_project -delete
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