Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
This commit is contained in:
Blaise Tine
1
hw/syn/altera/opae/.gitignore
vendored
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1
hw/syn/altera/opae/.gitignore
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build*/*
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148
hw/syn/altera/opae/Makefile
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148
hw/syn/altera/opae/Makefile
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DEVICE_FAMILY ?= arria10
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XLEN ?= 32
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PREFIX ?= build$(XLEN)
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TARGET ?= fpga
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NUM_CORES ?= 1
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SCRIPT_DIR = ../../../scripts
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RTL_DIR = ../../../rtl
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DPI_DIR = ../../../dpi
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AFU_DIR = $(RTL_DIR)/afu/opae
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THIRD_PARTY_DIR = ../../../../third_party
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IP_CACHE_DIR = ../ip_cache/$(DEVICE_FAMILY)
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BUILD_DIR = $(PREFIX)_$(DEVICE_FAMILY)_$(TARGET)_$(NUM_CORES)c
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ifeq ($(shell which qsub-synth),)
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RUN_SYNTH=$(OPAE_PLATFORM_ROOT)/bin/run.sh > build.log 2>&1 &
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else
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RUN_SYNTH=qsub-synth
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endif
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# control RTL debug tracing states
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_ICACHE
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_DCACHE
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DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_MEM
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DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_BANK
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DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_MSHR
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DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_TAG
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DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_DATA
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DBG_TRACE_FLAGS += -DDBG_TRACE_AFU
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DBG_TRACE_FLAGS += -DDBG_TRACE_GBAR
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# Control logic analyzer monitors
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DBG_SCOPE_FLAGS += -DDBG_SCOPE_AFU
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DBG_SCOPE_FLAGS += -DDBG_SCOPE_ISSUE
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DBG_SCOPE_FLAGS += -DDBG_SCOPE_FETCH
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DBG_SCOPE_FLAGS += -DDBG_SCOPE_LSU
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DBG_SCOPE_FLAGS += -DDBG_SCOPE_MSCHED
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ifeq ($(DEVICE_FAMILY), stratix10)
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CONFIGS += -DALTERA_S10
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endif
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ifeq ($(DEVICE_FAMILY), arria10)
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CONFIGS += -DALTERA_A10
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endif
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# cluster configuration
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CONFIGS_1c := -DNUM_CLUSTERS=1 -DNUM_CORES=1
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CONFIGS_2c := -DNUM_CLUSTERS=1 -DNUM_CORES=2
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CONFIGS_4c := -DNUM_CLUSTERS=1 -DNUM_CORES=4
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CONFIGS_8c := -DNUM_CLUSTERS=1 -DNUM_CORES=8
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CONFIGS_16c := -DNUM_CLUSTERS=1 -DNUM_CORES=16 -DL2_ENABLE
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CONFIGS_32c := -DNUM_CLUSTERS=2 -DNUM_CORES=16 -DL2_ENABLE
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CONFIGS_64c := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE
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CONFIGS += $(CONFIGS_$(NUM_CORES)c)
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# include paths
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FPU_INCLUDE = -I$(RTL_DIR)/fpu
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ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
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FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
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endif
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RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(IP_CACHE_DIR)
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RTL_INCLUDE += $(FPU_INCLUDE)
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# compilation flags
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CFLAGS += -DSYNTHESIS -DQUARTUS
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CFLAGS += -DXLEN_$(XLEN)
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CFLAGS += $(CONFIGS)
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CFLAGS += $(RTL_INCLUDE)
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ifneq ($(TARGET), fpga)
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CFLAGS += -DSIMULATION
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endif
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# Debugigng
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ifdef DEBUG
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ifeq ($(TARGET), fpga)
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CFLAGS += -DNDEBUG -DSCOPE $(DBG_SCOPE_FLAGS)
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SCOPE_JSON += $(BUILD_DIR)/scope.json
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else
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CFLAGS += $(DBG_TRACE_FLAGS)
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endif
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else
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CFLAGS += -DNDEBUG
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endif
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# Enable scope analyzer
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ifdef SCOPE
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CFLAGS += -DSCOPE
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endif
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# Enable perf counters
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ifdef PERF
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CFLAGS += -DPERF_ENABLE
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endif
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# ast dump flags
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XML_CFLAGS = $(filter-out -DSYNTHESIS -DQUARTUS, $(CFLAGS)) -I$(AFU_DIR)/ccip -I$(DPI_DIR) -DNOPAE
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all: swconfig ip-gen setup build
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ip-gen: $(IP_CACHE_DIR)/ip-gen.log
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$(IP_CACHE_DIR)/ip-gen.log:
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../ip_gen.sh $(IP_CACHE_DIR)
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swconfig: vortex_afu.h
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vortex_afu.h: vortex_afu.json
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afu_json_mgr json-info --afu-json=$^ --c-hdr=$@
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$(BUILD_DIR)/setup.cfg:
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mkdir -p $(BUILD_DIR); cp setup.cfg $(BUILD_DIR)/setup.cfg
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$(BUILD_DIR)/vortex_afu.qsf:
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mkdir -p $(BUILD_DIR); cp vortex_afu.qsf $(BUILD_DIR)/vortex_afu.qsf
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$(BUILD_DIR)/vortex_afu.json:
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mkdir -p $(BUILD_DIR); cp vortex_afu.json $(BUILD_DIR)/vortex_afu.json
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gen-sources: $(BUILD_DIR)/sources.txt
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$(BUILD_DIR)/sources.txt:
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mkdir -p $(BUILD_DIR); $(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) -C$(BUILD_DIR)/src -O$(BUILD_DIR)/sources.txt
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setup: $(BUILD_DIR)/synth
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$(BUILD_DIR)/synth: $(BUILD_DIR)/sources.txt $(BUILD_DIR)/setup.cfg $(BUILD_DIR)/vortex_afu.qsf $(BUILD_DIR)/vortex_afu.json
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ifeq ($(TARGET), asesim)
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afu_sim_setup -s $(BUILD_DIR)/setup.cfg $(BUILD_DIR)/synth
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else
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afu_synth_setup -s $(BUILD_DIR)/setup.cfg $(BUILD_DIR)/synth
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endif
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build: ip-gen setup $(SCOPE_JSON)
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ifeq ($(TARGET), asesim)
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make -C $(BUILD_DIR)/synth > $(BUILD_DIR)/synth/build.log 2>&1 &
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else
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cd $(BUILD_DIR)/synth && $(RUN_SYNTH)
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endif
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gen-ast: $(BUILD_DIR)/vortex.xml
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$(BUILD_DIR)/vortex.xml: setup
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verilator --xml-only -O0 $(XML_CFLAGS) vortex_afu.sv --xml-output $(BUILD_DIR)/vortex.xml
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scope-json: $(BUILD_DIR)/scope.json
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$(BUILD_DIR)/scope.json: $(BUILD_DIR)/vortex.xml
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$(SCRIPT_DIR)/scope.py $(BUILD_DIR)/vortex.xml -o $(BUILD_DIR)/scope.json
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clean:
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rm -rf vortex_afu.h $(BUILD_DIR)
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19
hw/syn/altera/opae/fpga_prog.sh
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19
hw/syn/altera/opae/fpga_prog.sh
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#!/bin/bash
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# Copyright © 2019-2023
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# FPGA programming
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# first argument is the bitstream
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fpgaconf --bus 0xaf $1
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52
hw/syn/altera/opae/run_ase.sh
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52
hw/syn/altera/opae/run_ase.sh
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#!/bin/bash
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# Copyright © 2019-2023
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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SCRIPT_DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )"
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BUILD_DIR=$1
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PROGRAM=$(basename "$2")
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PROGRAM_DIR=`dirname $2`
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VORTEX_RT_PATH=$SCRIPT_DIR/../../../../runtime
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# Export ASE_WORKDIR variable
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export ASE_WORKDIR=$SCRIPT_DIR/$BUILD_DIR/work
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shift 2
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# cleanup incomplete runs
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rm -f $ASE_WORKDIR/.app_lock.pid
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rm -f $ASE_WORKDIR/.ase_ready.pid
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rm -f $SCRIPT_DIR/$BUILD_DIR/nohup.out
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# Start Simulator in background
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pushd $SCRIPT_DIR/$BUILD_DIR
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echo " [DBG] starting ASE simnulator (stdout saved to '$SCRIPT_DIR/$BUILD_DIR/nohup.out')"
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nohup make sim &
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popd
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# Wait for simulator readiness
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# When .ase_ready is created in the $ASE_WORKDIR, ASE is ready for simulation
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while [ ! -f $ASE_WORKDIR/.ase_ready.pid ]
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do
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sleep 1
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done
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# run application
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pushd $PROGRAM_DIR
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echo " [DBG] running ./$PROGRAM $*"
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ASE_LOG=0 LD_LIBRARY_PATH=$POCL_RT_PATH/lib:$VORTEX_RT_PATH/opae:$LD_LIBRARY_PATH ./$PROGRAM $*
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popd
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4
hw/syn/altera/opae/setup.cfg
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4
hw/syn/altera/opae/setup.cfg
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vortex_afu.json
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QI:vortex_afu.qsf
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C:sources.txt
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54
hw/syn/altera/opae/vortex_afu.json
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54
hw/syn/altera/opae/vortex_afu.json
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{
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"version": 1,
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"afu-image": {
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"power": 0,
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"clock-frequency-high": "auto-200",
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"clock-frequency-low": "auto-100",
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"cmd-mem-read": 1,
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"cmd-mem-write": 2,
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"cmd-run": 3,
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"cmd-dcr-write": 4,
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"cmd-max-value": 4,
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"mmio-cmd-type": 10,
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"mmio-cmd-arg0": 12,
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"mmio-cmd-arg1": 14,
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"mmio-cmd-arg2": 16,
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"mmio-status": 18,
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"mmio-scope-read": 20,
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"mmio-scope-write": 22,
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"mmio-dev-caps": 24,
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"mmio-isa-caps": 26,
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"afu-top-interface":
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{
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"class": "ccip_std_afu_avalon_mm",
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"module-ports" :
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[
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{
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"class": "cci-p",
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"params":
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{
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"clock": "uClk_usr"
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}
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},
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{
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"class": "local-memory",
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"params":
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{
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"clock": "uClk_usr"
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}
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}
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]
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},
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"accelerator-clusters":
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[
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{
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"name": "vortex_afu",
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"total-contexts": 1,
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"accelerator-type-uuid": "35f9452b-25c2-434c-93d5-6f8c60db361c"
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}
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]
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}
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}
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36
hw/syn/altera/opae/vortex_afu.qsf
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36
hw/syn/altera/opae/vortex_afu.qsf
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# Analysis & Synthesis Assignments
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
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set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON
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set_global_assignment -name MESSAGE_DISABLE 16818
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set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
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set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
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set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
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set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
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set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
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set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
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set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
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set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
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set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
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set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
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#set_global_assignment -name USE_HIGH_SPEED_ADDER ON
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#set_global_assignment -name MUX_RESTRUCTURE ON
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#set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
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#set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "FORCE ALL TILES WITH FAILING TIMING PATHS TO HIGH SPEED"
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#set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
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#set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
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#set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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#set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
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#set_global_assignment -name SEED 1
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