Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
This commit is contained in:
Blaise Tine
@@ -1,252 +1,60 @@
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_sp_ram #(
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parameter DATAW = 1,
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parameter SIZE = 1,
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parameter BYTEENW = 1,
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parameter WRENW = 1,
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parameter OUT_REG = 0,
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parameter NO_RWCHECK = 0,
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parameter LUTRAM = 0,
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parameter ADDRW = $clog2(SIZE),
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parameter LUTRAM = 0,
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parameter INIT_ENABLE = 0,
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parameter INIT_FILE = "",
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parameter [DATAW-1:0] INIT_VALUE = 0
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parameter [DATAW-1:0] INIT_VALUE = 0,
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parameter ADDRW = `LOG2UP(SIZE)
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) (
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input wire clk,
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input wire clk,
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input wire read,
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input wire write,
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input wire [WRENW-1:0] wren,
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input wire [ADDRW-1:0] addr,
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input wire [BYTEENW-1:0] wren,
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input wire [DATAW-1:0] wdata,
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output wire [DATAW-1:0] rdata
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);
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`STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter"))
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`define RAM_INITIALIZATION \
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if (INIT_ENABLE) begin \
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if (INIT_FILE != "") begin \
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initial $readmemh(INIT_FILE, ram); \
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end else begin \
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initial \
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for (integer i = 0; i < SIZE; ++i)\
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ram[i] = INIT_VALUE; \
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end \
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end
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`ifdef SYNTHESIS
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if (LUTRAM) begin
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if (OUT_REG) begin
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reg [DATAW-1:0] rdata_r;
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if (BYTEENW > 1) begin
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`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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for (integer i = 0; i < BYTEENW; i++) begin
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if (wren[i])
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ram[addr][i] <= wdata[i * 8 +: 8];
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end
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rdata_r <= ram[addr];
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end
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end else begin
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`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (wren)
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ram[addr] <= wdata;
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rdata_r <= ram[addr];
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end
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end
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assign rdata = rdata_r;
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end else begin
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if (BYTEENW > 1) begin
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`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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for (integer i = 0; i < BYTEENW; i++) begin
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if (wren[i])
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ram[addr][i] <= wdata[i * 8 +: 8];
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end
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end
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assign rdata = ram[addr];
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end else begin
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`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (wren)
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ram[addr] <= wdata;
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end
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assign rdata = ram[addr];
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end
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end
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end else begin
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if (OUT_REG) begin
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reg [DATAW-1:0] rdata_r;
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if (BYTEENW > 1) begin
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reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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for (integer i = 0; i < BYTEENW; i++) begin
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if (wren[i])
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ram[addr][i] <= wdata[i * 8 +: 8];
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end
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rdata_r <= ram[addr];
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end
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end else begin
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reg [DATAW-1:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (wren)
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ram[addr] <= wdata;
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rdata_r <= ram[addr];
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end
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end
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assign rdata = rdata_r;
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end else begin
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if (NO_RWCHECK) begin
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if (BYTEENW > 1) begin
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`NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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for (integer i = 0; i < BYTEENW; i++) begin
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if (wren[i])
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ram[addr][i] <= wdata[i * 8 +: 8];
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end
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end
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assign rdata = ram[addr];
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end else begin
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`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (wren)
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ram[addr] <= wdata;
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end
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assign rdata = ram[addr];
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end
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end else begin
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if (BYTEENW > 1) begin
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reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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for (integer i = 0; i < BYTEENW; i++) begin
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if (wren[i])
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ram[addr][i] <= wdata[i * 8 +: 8];
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end
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end
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assign rdata = ram[addr];
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end else begin
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reg [DATAW-1:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (wren)
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ram[addr] <= wdata;
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end
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assign rdata = ram[addr];
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end
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end
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end
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end
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`else
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if (OUT_REG) begin
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reg [DATAW-1:0] rdata_r;
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if (BYTEENW > 1) begin
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reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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for (integer i = 0; i < BYTEENW; i++) begin
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if (wren[i])
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ram[addr][i] <= wdata[i * 8 +: 8];
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end
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rdata_r <= ram[addr];
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end
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end else begin
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reg [DATAW-1:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (wren)
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ram[addr] <= wdata;
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rdata_r <= ram[addr];
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end
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end
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assign rdata = rdata_r;
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end else begin
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if (BYTEENW > 1) begin
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reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
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reg [DATAW-1:0] prev_data;
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reg [ADDRW-1:0] prev_addr;
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reg prev_write;
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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for (integer i = 0; i < BYTEENW; i++) begin
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if (wren[i])
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ram[addr][i] <= wdata[i * 8 +: 8];
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end
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prev_write <= (| wren);
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prev_data <= ram[addr];
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prev_addr <= addr;
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end
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if (LUTRAM || !NO_RWCHECK) begin
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`UNUSED_VAR (prev_write)
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`UNUSED_VAR (prev_data)
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`UNUSED_VAR (prev_addr)
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assign rdata = ram[addr];
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end else begin
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assign rdata = (prev_write && (prev_addr == addr)) ? prev_data : ram[addr];
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end
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end else begin
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reg [DATAW-1:0] ram [SIZE-1:0];
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reg [DATAW-1:0] prev_data;
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reg [ADDRW-1:0] prev_addr;
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reg prev_write;
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (wren)
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ram[addr] <= wdata;
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prev_write <= wren;
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prev_data <= ram[addr];
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prev_addr <= addr;
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end
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if (LUTRAM || !NO_RWCHECK) begin
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`UNUSED_VAR (prev_write)
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`UNUSED_VAR (prev_data)
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`UNUSED_VAR (prev_addr)
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assign rdata = ram[addr];
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end else begin
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assign rdata = (prev_write && (prev_addr == addr)) ? prev_data : ram[addr];
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end
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end
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end
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`endif
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VX_dp_ram #(
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.DATAW (DATAW),
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.SIZE (SIZE),
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.WRENW (WRENW),
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.OUT_REG (OUT_REG),
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.NO_RWCHECK (NO_RWCHECK),
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.LUTRAM (LUTRAM),
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.INIT_ENABLE (INIT_ENABLE),
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.INIT_FILE (INIT_FILE),
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.INIT_VALUE (INIT_VALUE),
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.ADDRW (ADDRW)
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) dp_ram (
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.clk (clk),
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.read (read),
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.write (write),
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.wren (wren),
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.waddr (addr),
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.wdata (wdata),
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.raddr (addr),
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.rdata (rdata)
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);
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endmodule
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`TRACING_ON
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`TRACING_ON
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