Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
This commit is contained in:
Blaise Tine
@@ -1,3 +1,16 @@
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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@@ -5,23 +18,23 @@ module VX_rr_arbiter #(
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parameter NUM_REQS = 1,
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parameter LOCK_ENABLE = 0,
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parameter MODEL = 1,
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parameter LOG_NUM_REQS = $clog2(NUM_REQS)
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parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
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) (
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input wire clk,
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input wire reset,
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input wire enable,
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input wire unlock,
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input wire [NUM_REQS-1:0] requests,
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output wire [LOG_NUM_REQS-1:0] grant_index,
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output wire [NUM_REQS-1:0] grant_onehot,
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output wire grant_valid
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);
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);
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if (NUM_REQS == 1) begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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`UNUSED_VAR (unlock)
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assign grant_index = 0;
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assign grant_index = '0;
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assign grant_onehot = requests;
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assign grant_valid = requests[0];
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@@ -41,8 +54,8 @@ module VX_rr_arbiter #(
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always @(posedge clk) begin
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if (reset) begin
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state <= 0;
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end else if (!LOCK_ENABLE || enable) begin
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state <= '0;
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end else if (!LOCK_ENABLE || unlock) begin
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state <= grant_index_r;
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end
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end
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@@ -51,7 +64,37 @@ module VX_rr_arbiter #(
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assign grant_onehot = grant_onehot_r;
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assign grant_valid = (| requests);
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end else if (NUM_REQS == 4) begin
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end /*else if (NUM_REQS == 3) begin
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reg [LOG_NUM_REQS-1:0] grant_index_r;
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reg [NUM_REQS-1:0] grant_onehot_r;
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reg [LOG_NUM_REQS-1:0] state;
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always @(*) begin
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casez ({state, requests})
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5'b00_001,
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5'b01_0?1,
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5'b10_??1: begin grant_onehot_r = 3'b001; grant_index_r = LOG_NUM_REQS'(0); end
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5'b00_?1?,
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5'b01_010,
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5'b10_?10: begin grant_onehot_r = 3'b010; grant_index_r = LOG_NUM_REQS'(1); end
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default: begin grant_onehot_r = 3'b100; grant_index_r = LOG_NUM_REQS'(2); end
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endcase
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end
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always @(posedge clk) begin
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if (reset) begin
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state <= '0;
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end else if (!LOCK_ENABLE || unlock) begin
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state <= grant_index_r;
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end
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end
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assign grant_index = grant_index_r;
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assign grant_onehot = grant_onehot_r;
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assign grant_valid = (| requests);
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end */else if (NUM_REQS == 4) begin
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reg [LOG_NUM_REQS-1:0] grant_index_r;
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reg [NUM_REQS-1:0] grant_onehot_r;
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@@ -77,8 +120,8 @@ module VX_rr_arbiter #(
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always @(posedge clk) begin
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if (reset) begin
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state <= 0;
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end else if (!LOCK_ENABLE || enable) begin
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state <= '0;
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end else if (!LOCK_ENABLE || unlock) begin
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state <= grant_index_r;
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end
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end
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@@ -87,7 +130,171 @@ module VX_rr_arbiter #(
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assign grant_onehot = grant_onehot_r;
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assign grant_valid = (| requests);
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end else if (NUM_REQS == 8) begin
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end /*else if (NUM_REQS == 5) begin
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reg [LOG_NUM_REQS-1:0] grant_index_r;
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reg [NUM_REQS-1:0] grant_onehot_r;
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reg [LOG_NUM_REQS-1:0] state;
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always @(*) begin
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casez ({state, requests})
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8'b000_00001,
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8'b001_000?1,
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8'b010_00??1,
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8'b011_0???1,
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8'b100_????1: begin grant_onehot_r = 5'b00001; grant_index_r = LOG_NUM_REQS'(0); end
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8'b000_???1?,
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8'b001_00010,
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8'b010_00?10,
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8'b011_0??10,
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8'b100_???10: begin grant_onehot_r = 5'b00010; grant_index_r = LOG_NUM_REQS'(1); end
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8'b000_??10?,
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8'b001_??1??,
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8'b010_00100,
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8'b011_0?100,
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8'b100_??100: begin grant_onehot_r = 5'b00100; grant_index_r = LOG_NUM_REQS'(2); end
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8'b000_?100?,
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8'b001_?10??,
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8'b010_?1???,
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8'b011_01000,
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8'b100_?1000: begin grant_onehot_r = 5'b01000; grant_index_r = LOG_NUM_REQS'(3); end
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default: begin grant_onehot_r = 5'b10000; grant_index_r = LOG_NUM_REQS'(4); end
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endcase
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end
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always @(posedge clk) begin
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if (reset) begin
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state <= '0;
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end else if (!LOCK_ENABLE || unlock) begin
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state <= grant_index_r;
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end
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end
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assign grant_index = grant_index_r;
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assign grant_onehot = grant_onehot_r;
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assign grant_valid = (| requests);
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end else if (NUM_REQS == 6) begin
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reg [LOG_NUM_REQS-1:0] grant_index_r;
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reg [NUM_REQS-1:0] grant_onehot_r;
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reg [LOG_NUM_REQS-1:0] state;
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always @(*) begin
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casez ({state, requests})
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9'b000_000001,
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9'b001_0000?1,
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9'b010_000??1,
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9'b011_00???1,
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9'b100_0????1,
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9'b101_?????1: begin grant_onehot_r = 6'b000001; grant_index_r = LOG_NUM_REQS'(0); end
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9'b000_????1?,
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9'b001_000010,
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9'b010_000?10,
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9'b011_00??10,
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9'b100_0???10,
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9'b101_????10: begin grant_onehot_r = 6'b000010; grant_index_r = LOG_NUM_REQS'(1); end
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9'b000_???10?,
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9'b001_???1??,
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9'b010_000100,
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9'b011_00?100,
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9'b100_0??100,
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9'b101_???100: begin grant_onehot_r = 6'b000100; grant_index_r = LOG_NUM_REQS'(2); end
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9'b000_??100?,
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9'b001_??10??,
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9'b010_??1???,
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9'b011_001000,
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9'b100_0?1000,
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9'b101_??1000: begin grant_onehot_r = 6'b001000; grant_index_r = LOG_NUM_REQS'(3); end
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9'b000_?1000?,
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9'b001_?100??,
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9'b010_?10???,
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9'b011_?1????,
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9'b100_010000,
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9'b101_?10000: begin grant_onehot_r = 6'b010000; grant_index_r = LOG_NUM_REQS'(4); end
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default: begin grant_onehot_r = 6'b100000; grant_index_r = LOG_NUM_REQS'(5); end
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endcase
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end
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always @(posedge clk) begin
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if (reset) begin
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state <= '0;
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end else if (!LOCK_ENABLE || unlock) begin
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state <= grant_index_r;
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end
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end
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assign grant_index = grant_index_r;
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assign grant_onehot = grant_onehot_r;
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assign grant_valid = (| requests);
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end else if (NUM_REQS == 7) begin
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reg [LOG_NUM_REQS-1:0] grant_index_r;
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reg [NUM_REQS-1:0] grant_onehot_r;
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reg [LOG_NUM_REQS-1:0] state;
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always @(*) begin
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casez ({state, requests})
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10'b000_000001,
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10'b001_0000?1,
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10'b010_000??1,
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10'b011_00???1,
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10'b100_00???1,
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10'b101_0????1,
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10'b110_?????1: begin grant_onehot_r = 7'b0000001; grant_index_r = LOG_NUM_REQS'(0); end
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10'b000_?????1?,
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10'b001_0000010,
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10'b010_0000?10,
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10'b011_000??10,
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10'b100_00???10,
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10'b101_0????10,
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10'b110_?????10: begin grant_onehot_r = 7'b0000010; grant_index_r = LOG_NUM_REQS'(1); end
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10'b000_????10?,
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10'b001_????1??,
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10'b010_0000100,
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10'b011_000?100,
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10'b100_00??100,
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10'b101_0???100,
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10'b110_????100: begin grant_onehot_r = 7'b0000100; grant_index_r = LOG_NUM_REQS'(2); end
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10'b000_???100?,
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10'b001_???10??,
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10'b010_???1???,
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10'b011_0001000,
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10'b100_00?1000,
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10'b101_0??1000,
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10'b110_???1000: begin grant_onehot_r = 7'b0001000; grant_index_r = LOG_NUM_REQS'(3); end
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10'b000_??1000?,
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10'b001_??100??,
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10'b010_??10???,
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10'b011_??1????,
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10'b100_0010000,
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10'b101_0?10000,
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10'b110_??10000: begin grant_onehot_r = 7'b0010000; grant_index_r = LOG_NUM_REQS'(4); end
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10'b000_?10000?,
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10'b001_?1000??,
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10'b010_?100???,
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10'b011_?10????,
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10'b100_?1?????,
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10'b101_0100000,
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10'b110_?100000: begin grant_onehot_r = 7'b0100000; grant_index_r = LOG_NUM_REQS'(5); end
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default: begin grant_onehot_r = 7'b1000000; grant_index_r = LOG_NUM_REQS'(6); end
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endcase
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end
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always @(posedge clk) begin
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if (reset) begin
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state <= '0;
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end else if (!LOCK_ENABLE || unlock) begin
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state <= grant_index_r;
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end
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end
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assign grant_index = grant_index_r;
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assign grant_onehot = grant_onehot_r;
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assign grant_valid = (| requests);
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end */else if (NUM_REQS == 8) begin
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reg [LOG_NUM_REQS-1:0] grant_index_r;
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reg [NUM_REQS-1:0] grant_onehot_r;
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@@ -157,8 +364,8 @@ module VX_rr_arbiter #(
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always @(posedge clk) begin
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if (reset) begin
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state <= 0;
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end else if (!LOCK_ENABLE || enable) begin
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state <= '0;
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end else if (!LOCK_ENABLE || unlock) begin
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state <= grant_index_r;
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end
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end
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@@ -169,9 +376,9 @@ module VX_rr_arbiter #(
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end else if (MODEL == 1) begin
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`IGNORE_WARNINGS_BEGIN
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`IGNORE_UNOPTFLAT_BEGIN
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wire [NUM_REQS-1:0] mask_higher_pri_regs, unmask_higher_pri_regs;
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`IGNORE_WARNINGS_END
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`IGNORE_UNOPTFLAT_END
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wire [NUM_REQS-1:0] grant_masked, grant_unmasked;
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reg [NUM_REQS-1:0] pointer_reg;
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@@ -192,7 +399,7 @@ module VX_rr_arbiter #(
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always @(posedge clk) begin
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if (reset) begin
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pointer_reg <= {NUM_REQS{1'b1}};
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end else if (!LOCK_ENABLE || enable) begin
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end else if (!LOCK_ENABLE || unlock) begin
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if (|req_masked) begin
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pointer_reg <= mask_higher_pri_regs;
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end else if (|requests) begin
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@@ -235,8 +442,8 @@ module VX_rr_arbiter #(
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always @(posedge clk) begin
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if (reset) begin
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state <= 0;
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end else if (!LOCK_ENABLE || enable) begin
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state <= '0;
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end else if (!LOCK_ENABLE || unlock) begin
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state <= grant_index_r;
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end
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end
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@@ -247,4 +454,4 @@ module VX_rr_arbiter #(
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end
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endmodule
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`TRACING_ON
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`TRACING_ON
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