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Vortex 2.0 changes:

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+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes

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cleanup

cleanup

cache bindings and memory perf refactory

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hw unit tests fixes

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This commit is contained in:
Blaise Tine
2023-10-19 20:51:22 -07:00
parent d69a64c32c
commit c1e168fdbe
1309 changed files with 247412 additions and 311463 deletions
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78
hw/rtl/libs/VX_multiplier.sv
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@@ -1,70 +1,54 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_platform.vh"
`TRACING_OFF
module VX_multiplier #(
parameter WIDTHA = 1,
parameter WIDTHB = 1,
parameter WIDTHP = 1,
parameter A_WIDTH = 1,
parameter B_WIDTH = A_WIDTH,
parameter R_WIDTH = A_WIDTH + B_WIDTH,
parameter SIGNED = 0,
parameter LATENCY = 0
) (
input wire clk,
input wire enable,
input wire [WIDTHA-1:0] dataa,
input wire [WIDTHB-1:0] datab,
output wire [WIDTHP-1:0] result
input wire [A_WIDTH-1:0] dataa,
input wire [B_WIDTH-1:0] datab,
output wire [R_WIDTH-1:0] result
);
wire [R_WIDTH-1:0] prod_w;
`ifdef QUARTUS
lpm_mult mult (
.clock (clk),
.clken (enable),
.dataa (dataa),
.datab (datab),
.result (result),
.aclr (1'b0),
.sclr (1'b0),
.sum (1'b0)
);
defparam mult.lpm_type = "LPM_MULT",
mult.lpm_widtha = WIDTHA,
mult.lpm_widthb = WIDTHB,
mult.lpm_widthp = WIDTHP,
mult.lpm_representation = SIGNED ? "SIGNED" : "UNSIGNED",
mult.lpm_pipeline = LATENCY,
mult.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9";
`else
wire [WIDTHP-1:0] result_unqual;
if (SIGNED) begin
assign result_unqual = $signed(dataa) * $signed(datab);
if (SIGNED != 0) begin
assign prod_w = R_WIDTH'($signed(dataa) * $signed(datab));
end else begin
assign result_unqual = dataa * datab;
assign prod_w = R_WIDTH'(dataa * datab);
end
if (LATENCY == 0) begin
assign result = result_unqual;
assign result = prod_w;
end else begin
reg [WIDTHP-1:0] result_pipe [LATENCY-1:0];
reg [LATENCY-1:0][R_WIDTH-1:0] prod_r;
always @(posedge clk) begin
if (enable) begin
result_pipe[0] <= result_unqual;
end
end
for (genvar i = 1; i < LATENCY; i++) begin
always @(posedge clk) begin
if (enable) begin
result_pipe[i] <= result_pipe[i-1];
prod_r[0] <= prod_w;
for (integer i = 1; i < LATENCY; ++i) begin
prod_r[i] <= prod_r[i-1];
end
end
end
assign result = result_pipe[LATENCY-1];
end
assign result = prod_r[LATENCY-1];
end
`endif
endmodule
`TRACING_ON
`TRACING_ON