Vortex 2.0 changes:

+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes

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cleanup

cleanup

cache bindings and memory perf refactory

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hw unit tests fixes

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minor udpate

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hw/rtl/libs/VX_index_queue.sv

@@ -1,20 +1,33 @@
+// Copyright © 2019-2023
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+// 
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
 `include "VX_platform.vh"
 
 `TRACING_OFF
 module VX_index_queue #(
     parameter DATAW = 1,
-    parameter SIZE = 1
+    parameter SIZE  = 1
 ) (
-    input  wire clk,
-    input  wire reset,
-    input  wire [DATAW-1:0] write_data,        
+    input  wire                     clk,
+    input  wire                     reset,
+    input  wire [DATAW-1:0]         write_data,        
     output wire [`LOG2UP(SIZE)-1:0] write_addr,
-    input  wire push,    
-    input  wire pop,
-    output wire full,
-    output wire empty,
+    input  wire                     push,    
+    input  wire                     pop,
+    output wire                     full,
+    output wire                     empty,
     input  wire [`LOG2UP(SIZE)-1:0] read_addr,
-    output wire [DATAW-1:0] read_data
+    output wire [DATAW-1:0]         read_data
 );
     reg [DATAW-1:0] entries [SIZE-1:0];
     reg [SIZE-1:0] valid;    
@@ -36,9 +49,9 @@ module VX_index_queue #(
     
     always @(posedge clk) begin
         if (reset) begin
-            rd_ptr <= 0;
-            wr_ptr <= 0;
-            valid  <= 0;     
+            rd_ptr <= '0;
+            wr_ptr <= '0;
+            valid  <= '0;     
         end else begin
             if (enqueue)  begin
                 valid[wr_a] <= 1;
@@ -61,4 +74,4 @@ module VX_index_queue #(
     assign read_data = entries[read_addr];
 
 endmodule
-`TRACING_ON
+`TRACING_ON