Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
This commit is contained in:
Blaise Tine
@@ -1,15 +1,27 @@
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_fifo_queue #(
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parameter DATAW = 1,
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parameter SIZE = 2,
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parameter ALM_FULL = (SIZE - 1),
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parameter DEPTH = 2,
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parameter ALM_FULL = (DEPTH - 1),
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parameter ALM_EMPTY = 1,
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parameter ADDRW = $clog2(SIZE),
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parameter SIZEW = $clog2(SIZE+1),
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parameter OUT_REG = 0,
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parameter LUTRAM = 1
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parameter LUTRAM = 1,
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parameter SIZEW = `CLOG2(DEPTH+1)
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) (
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input wire clk,
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input wire reset,
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@@ -23,26 +35,33 @@ module VX_fifo_queue #(
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output wire alm_full,
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output wire [SIZEW-1:0] size
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);
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`STATIC_ASSERT(`ISPOW2(SIZE), ("must be 0 or power of 2!"))
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if (SIZE == 1) begin
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localparam ADDRW = `CLOG2(DEPTH);
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`STATIC_ASSERT(ALM_FULL > 0, ("alm_full must be greater than 0!"))
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`STATIC_ASSERT(ALM_FULL < DEPTH, ("alm_full must be smaller than size!"))
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`STATIC_ASSERT(ALM_EMPTY > 0, ("alm_empty must be greater than 0!"))
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`STATIC_ASSERT(ALM_EMPTY < DEPTH, ("alm_empty must be smaller than size!"))
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`STATIC_ASSERT(`ISPOW2(DEPTH), ("size must be a power of 2!"))
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if (DEPTH == 1) begin
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reg [DATAW-1:0] head_r;
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reg size_r;
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always @(posedge clk) begin
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if (reset) begin
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head_r <= 0;
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size_r <= 0;
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head_r <= '0;
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size_r <= '0;
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end else begin
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`ASSERT(!push || !full, ("runtime error"));
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`ASSERT(!pop || !empty, ("runtime error"));
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`ASSERT(~push || ~full, ("runtime error: writing to a full queue"));
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`ASSERT(~pop || ~empty, ("runtime error: reading an empty queue"));
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if (push) begin
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if (!pop) begin
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if (~pop) begin
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size_r <= 1;
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end
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end else if (pop) begin
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size_r <= 0;
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size_r <= '0;
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end
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if (push) begin
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head_r <= data_in;
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@@ -62,6 +81,7 @@ module VX_fifo_queue #(
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reg empty_r, alm_empty_r;
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reg full_r, alm_full_r;
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reg [ADDRW-1:0] used_r;
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wire [ADDRW-1:0] used_n;
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always @(posedge clk) begin
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if (reset) begin
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@@ -69,43 +89,40 @@ module VX_fifo_queue #(
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alm_empty_r <= 1;
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full_r <= 0;
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alm_full_r <= 0;
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used_r <= 0;
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used_r <= '0;
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end else begin
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`ASSERT(!push || !full, ("runtime error"));
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`ASSERT(!pop || !empty, ("runtime error"));
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`ASSERT(~(push && ~pop) || ~full, ("runtime error: incrementing full queue"));
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`ASSERT(~(pop && ~push) || ~empty, ("runtime error: decrementing empty queue"));
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if (push) begin
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if (!pop) begin
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if (~pop) begin
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empty_r <= 0;
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if (used_r == ADDRW'(ALM_EMPTY))
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alm_empty_r <= 0;
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if (used_r == ADDRW'(SIZE-1))
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if (used_r == ADDRW'(DEPTH-1))
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full_r <= 1;
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if (used_r == ADDRW'(ALM_FULL-1))
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alm_full_r <= 1;
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end
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end else if (pop) begin
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full_r <= 0;
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full_r <= 0;
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if (used_r == ADDRW'(ALM_FULL))
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alm_full_r <= 0;
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if (used_r == ADDRW'(1))
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empty_r <= 1;
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if (used_r == ADDRW'(ALM_EMPTY+1))
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alm_empty_r <= 1;
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end
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if (SIZE > 2) begin
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used_r <= used_r + ADDRW'($signed(2'(push) - 2'(pop)));
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end else begin
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// (SIZE == 2);
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used_r[0] <= used_r[0] ^ (push ^ pop);
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end
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used_r <= used_n;
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end
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end
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if (SIZE == 2) begin
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if (DEPTH == 2) begin
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assign used_n = used_r ^ (push ^ pop);
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if (0 == OUT_REG) begin
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reg [DATAW-1:0] shift_reg [1:0];
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reg [1:0][DATAW-1:0] shift_reg;
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always @(posedge clk) begin
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if (push) begin
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@@ -137,6 +154,8 @@ module VX_fifo_queue #(
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end
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end else begin
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assign used_n = $signed(used_r) + ADDRW'($signed(2'(push) - 2'(pop)));
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if (0 == OUT_REG) begin
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@@ -145,8 +164,8 @@ module VX_fifo_queue #(
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always @(posedge clk) begin
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if (reset) begin
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rd_ptr_r <= 0;
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wr_ptr_r <= 0;
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rd_ptr_r <= '0;
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wr_ptr_r <= '0;
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end else begin
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wr_ptr_r <= wr_ptr_r + ADDRW'(push);
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rd_ptr_r <= rd_ptr_r + ADDRW'(pop);
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@@ -154,13 +173,14 @@ module VX_fifo_queue #(
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end
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VX_dp_ram #(
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.DATAW (DATAW),
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.SIZE (SIZE),
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.OUT_REG (0),
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.LUTRAM (LUTRAM)
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.DATAW (DATAW),
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.SIZE (DEPTH),
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.LUTRAM (LUTRAM)
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) dp_ram (
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.clk(clk),
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.wren (push),
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.read (1'b1),
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.write (push),
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`UNUSED_PIN (wren),
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.waddr (wr_ptr_r),
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.wdata (data_in),
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.raddr (rd_ptr_r),
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@@ -177,8 +197,8 @@ module VX_fifo_queue #(
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always @(posedge clk) begin
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if (reset) begin
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wr_ptr_r <= 0;
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rd_ptr_r <= 0;
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wr_ptr_r <= '0;
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rd_ptr_r <= '0;
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rd_ptr_n_r <= 1;
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end else begin
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if (push) begin
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@@ -186,23 +206,31 @@ module VX_fifo_queue #(
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end
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if (pop) begin
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rd_ptr_r <= rd_ptr_n_r;
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if (SIZE > 2) begin
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if (DEPTH > 2) begin
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rd_ptr_n_r <= rd_ptr_r + ADDRW'(2);
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end else begin // (SIZE == 2);
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end else begin // (DEPTH == 2);
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rd_ptr_n_r <= ~rd_ptr_n_r;
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end
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end
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end
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end
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wire going_empty;
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if (ALM_EMPTY == 1) begin
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assign going_empty = alm_empty_r;
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end else begin
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assign going_empty = (used_r == ADDRW'(1));
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end
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VX_dp_ram #(
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.DATAW (DATAW),
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.SIZE (SIZE),
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.OUT_REG (0),
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.LUTRAM (LUTRAM)
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.DATAW (DATAW),
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.SIZE (DEPTH),
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.LUTRAM (LUTRAM)
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) dp_ram (
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.clk (clk),
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.wren (push),
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.read (1'b1),
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.write (push),
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`UNUSED_PIN (wren),
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.waddr (wr_ptr_r),
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.wdata (data_in),
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.raddr (rd_ptr_n_r),
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@@ -210,7 +238,7 @@ module VX_fifo_queue #(
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);
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always @(posedge clk) begin
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if (push && (empty_r || ((used_r == ADDRW'(1)) && pop))) begin
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if (push && (empty_r || (going_empty && pop))) begin
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dout_r <= data_in;
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end else if (pop) begin
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dout_r <= dout;
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@@ -229,4 +257,4 @@ module VX_fifo_queue #(
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end
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endmodule
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`TRACING_ON
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`TRACING_ON
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