Vortex 2.0 changes:

+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
2023-10-19 20:51:22 -07:00
parent d69a64c32c
commit c1e168fdbe
1309 changed files with 247412 additions and 311463 deletions
--- a/hw/rtl/interfaces/VX_writeback_if.sv
+++ b/hw/rtl/interfaces/VX_writeback_if.sv
@@ -1,44 +1,42 @@
-`ifndef VX_WRITEBACK_IF
-`define VX_WRITEBACK_IF
+// Copyright © 2019-2023
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+// 
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.

 `include "VX_define.vh"

-interface VX_writeback_if ();
+interface VX_writeback_if import VX_gpu_pkg::*; ();

-    wire                            valid;
-    wire [`UUID_BITS-1:0]           uuid;
-    wire [`NUM_THREADS-1:0]         tmask;
-    wire [`NW_BITS-1:0]             wid; 
-    wire [31:0]                     PC;
-    wire [`NR_BITS-1:0]             rd;
-    wire [`NUM_THREADS-1:0][31:0]   data;
-    wire                            eop;    
-    wire                            ready;
+    typedef struct packed {
+        logic [`UUID_WIDTH-1:0]         uuid;
+        logic [ISSUE_WIS_W-1:0]         wis;
+        logic [`NUM_THREADS-1:0]        tmask;
+        logic [`XLEN-1:0]               PC;
+        logic [`NR_BITS-1:0]            rd;
+        logic [`NUM_THREADS-1:0][`XLEN-1:0] data;
+        logic                           sop;
+        logic                           eop;
+    } data_t;
+
+    logic  valid;
+    data_t data;

    modport master (
        output valid,
-        output uuid,
-        output tmask,
-        output wid,
-        output PC,
-        output rd,
-        output data,
-        output eop,    
-        input  ready
+        output data
    );

    modport slave (
-        input  valid,
-        input  uuid,
-        input  tmask,
-        input  wid,
-        input  PC,
-        input  rd,
-        input  data,
-        input  eop,    
-        output ready
+        input valid,
+        input data
    );

 endinterface
-
-`endif