Vortex 2.0 changes:

+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
2023-10-19 20:51:22 -07:00
parent d69a64c32c
commit c1e168fdbe
1309 changed files with 247412 additions and 311463 deletions
--- a/hw/rtl/interfaces/VX_decode_if.sv
+++ b/hw/rtl/interfaces/VX_decode_if.sv
@@ -1,68 +1,56 @@
-`ifndef VX_DECODE_IF
-`define VX_DECODE_IF
+// Copyright © 2019-2023
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+// 
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.

 `include "VX_define.vh"

 interface VX_decode_if ();

-    wire                    valid;    
-    wire [`UUID_BITS-1:0]   uuid;
-    wire [`NW_BITS-1:0]     wid;
-    wire [`NUM_THREADS-1:0] tmask;
-    wire [31:0]             PC;
-    wire [`EX_BITS-1:0]     ex_type;    
-    wire [`INST_OP_BITS-1:0] op_type; 
-    wire [`INST_MOD_BITS-1:0] op_mod;    
-    wire                    wb;
-    wire                    use_PC;
-    wire                    use_imm;
-    wire [31:0]             imm;
-    wire [`NR_BITS-1:0]     rd;
-    wire [`NR_BITS-1:0]     rs1;
-    wire [`NR_BITS-1:0]     rs2;
-    wire [`NR_BITS-1:0]     rs3;
-    wire                    ready;
+    typedef struct packed {
+        logic [`UUID_WIDTH-1:0]     uuid;
+        logic [`NW_WIDTH-1:0]       wid;
+        logic [`NUM_THREADS-1:0]    tmask;
+        logic [`EX_BITS-1:0]        ex_type;    
+        logic [`INST_OP_BITS-1:0]   op_type;
+        logic [`INST_MOD_BITS-1:0]  op_mod;    
+        logic                       wb;
+        logic                       use_PC;
+        logic                       use_imm;
+        logic [`XLEN-1:0]           PC;
+        logic [`XLEN-1:0]           imm;
+        logic [`NR_BITS-1:0]        rd;
+        logic [`NR_BITS-1:0]        rs1;
+        logic [`NR_BITS-1:0]        rs2;
+        logic [`NR_BITS-1:0]        rs3;
+    } data_t;
+
+    logic  valid;
+    data_t data;
+    logic  ready;
+
+    wire [`ISSUE_WIDTH-1:0] ibuf_pop;

    modport master (
        output valid,
-        output uuid,
-        output wid,
-        output tmask,
-        output PC,
-        output ex_type,  
-        output op_type,
-        output op_mod,   
-        output wb,
-        output use_PC,
-        output use_imm,
-        output imm,
-        output rd,
-        output rs1,
-        output rs2,
-        output rs3,
+        output data,
+        input  ibuf_pop,
        input  ready
    );

    modport slave (
        input  valid,
-        input  uuid,
-        input  wid,
-        input  tmask,
-        input  PC,
-        input  ex_type,  
-        input  op_type,
-        input  op_mod,   
-        input  wb,
-        input  use_PC,
-        input  use_imm,
-        input  imm,
-        input  rd,
-        input  rs1,
-        input  rs2,
-        input  rs3,
+        input  data,
+        output ibuf_pop,
        output ready
    );

 endinterface
-
-`endif