Vortex 2.0 changes:

+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
2023-10-19 20:51:22 -07:00
parent d69a64c32c
commit c1e168fdbe
1309 changed files with 247412 additions and 311463 deletions
--- a/hw/rtl/interfaces/VX_commit_if.sv
+++ b/hw/rtl/interfaces/VX_commit_if.sv
@@ -1,47 +1,50 @@
-`ifndef VX_COMMIT_IF
-`define VX_COMMIT_IF
+// Copyright © 2019-2023
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+// 
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.

 `include "VX_define.vh"

-interface VX_commit_if ();
+interface VX_commit_if #(
+    parameter NUM_LANES = `NUM_THREADS,
+    parameter PID_WIDTH = `LOG2UP(`NUM_THREADS / NUM_LANES)
+) ();
+    
+    typedef struct packed {
+        logic [`UUID_WIDTH-1:0]     uuid;
+        logic [`NW_WIDTH-1:0]       wid;
+        logic [NUM_LANES-1:0]       tmask;
+        logic [`XLEN-1:0]           PC;
+        logic                       wb;
+        logic [`NR_BITS-1:0]        rd;
+        logic [NUM_LANES-1:0][`XLEN-1:0] data;
+        logic [PID_WIDTH-1:0]       pid;
+        logic                       sop;
+        logic                       eop;
+    } data_t;

-    wire                    valid;
-    wire [`UUID_BITS-1:0]   uuid;
-    wire [`NW_BITS-1:0]     wid;
-    wire [`NUM_THREADS-1:0] tmask;    
-    wire [31:0]             PC;
-    wire [`NUM_THREADS-1:0][31:0] data;
-    wire [`NR_BITS-1:0]     rd;
-    wire                    wb;
-    wire                    eop;
-    wire                    ready;
+    logic  valid;
+    data_t data;
+    logic  ready;    

    modport master (
        output valid,
-        output uuid,
-        output wid,
-        output tmask,
-        output PC,
        output data,
-        output rd,
-        output wb,
-        output eop,
        input  ready
    );

    modport slave (
        input  valid,
-        input  uuid,
-        input  wid,
-        input  tmask,
-        input  PC,
        input  data,
-        input  rd,
-        input  wb,
-        input  eop,
        output ready
    );

 endinterface
-
-`endif