Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
This commit is contained in:
Blaise Tine
419
hw/rtl/afu/xrt/VX_afu_ctrl.sv
Normal file
419
hw/rtl/afu/xrt/VX_afu_ctrl.sv
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "vortex_afu.vh"
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module VX_afu_ctrl #(
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parameter AXI_ADDR_WIDTH = 8,
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parameter AXI_DATA_WIDTH = 32,
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parameter AXI_NUM_BANKS = 1
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) (
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// axi4 lite slave signals
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input wire clk,
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input wire reset,
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input wire clk_en,
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input wire s_axi_awvalid,
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input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
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output wire s_axi_awready,
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input wire s_axi_wvalid,
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input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata,
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input wire [AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
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output wire s_axi_wready,
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output wire s_axi_bvalid,
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output wire [1:0] s_axi_bresp,
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input wire s_axi_bready,
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input wire s_axi_arvalid,
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input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr,
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output wire s_axi_arready,
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output wire s_axi_rvalid,
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output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata,
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output wire [1:0] s_axi_rresp,
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input wire s_axi_rready,
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output wire ap_reset,
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output wire ap_start,
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input wire ap_done,
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input wire ap_ready,
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input wire ap_idle,
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output wire interrupt,
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`ifdef SCOPE
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input wire scope_bus_in,
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output wire scope_bus_out,
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`endif
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output wire [63:0] mem_base [AXI_NUM_BANKS],
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output wire dcr_wr_valid,
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output wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr,
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output wire [`VX_DCR_DATA_WIDTH-1:0] dcr_wr_data
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);
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// Address Info
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// 0x00 : Control signals
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// bit 0 - ap_start (Read/Write/COH)
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// bit 1 - ap_done (Read/COR)
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// bit 2 - ap_idle (Read)
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// bit 3 - ap_ready (Read)
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// bit 4 - ap_reset (Write)
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// bit 7 - auto_restart (Read/Write)
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// others - reserved
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// 0x04 : Global Interrupt Enable Register
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// bit 0 - Global Interrupt Enable (Read/Write)
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// others - reserved
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// 0x08 : IP Interrupt Enable Register (Read/Write)
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// bit 0 - Channel 0 (ap_done)
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// bit 1 - Channel 1 (ap_ready)
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// others - reserved
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// 0x0c : IP Interrupt Status Register (Read/TOW)
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// bit 0 - Channel 0 (ap_done)
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// bit 1 - Channel 1 (ap_ready)
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// others - reserved
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// 0x10 : Low 32-bit Data signal of DEV_CAPS
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// 0x14 : High 32-bit Data signal of DEV_CAPS
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// 0x18 : Control signal of DEV_CAPS
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// 0x1C : Low 32-bit Data signal of ISA_CAPS
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// 0x20 : High 32-bit Data signal of ISA_CAPS
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// 0x24 : Control signal of ISA_CAPS
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// 0x28 : Low 32-bit Data signal of DCR
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// 0x2C : High 32-bit Data signal of DCR
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// 0x30 : Control signal of DCR
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// 0x34 : Low 32-bit Data signal of SCP
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// 0x38 : High 32-bit Data signal of SCP
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// 0x3C : Control signal of SCP
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// 0x40 : Low 32-bit Data signal of MEM
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// 0x44 : High 32-bit Data signal of MEM
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// 0x48 : Control signal of MEM
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// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
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// Parameters
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localparam
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ADDR_AP_CTRL = 8'h00,
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ADDR_GIE = 8'h04,
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ADDR_IER = 8'h08,
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ADDR_ISR = 8'h0C,
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ADDR_DEV_0 = 8'h10,
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ADDR_DEV_1 = 8'h14,
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ADDR_DEV_CTRL = 8'h18,
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ADDR_ISA_0 = 8'h1C,
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ADDR_ISA_1 = 8'h20,
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ADDR_ISA_CTRL = 8'h24,
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ADDR_DCR_0 = 8'h28,
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ADDR_DCR_1 = 8'h2C,
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ADDR_DCR_CTRL = 8'h30,
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ADDR_SCP_0 = 8'h34,
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ADDR_SCP_1 = 8'h38,
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ADDR_SCP_CTRL = 8'h3C,
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ADDR_MEM_0 = 8'h40,
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ADDR_MEM_1 = 8'h44,
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ADDR_MEM_CTRL = 8'h48,
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ADDR_BITS = 8;
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localparam
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WSTATE_IDLE = 2'd0,
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WSTATE_DATA = 2'd1,
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WSTATE_RESP = 2'd2;
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localparam
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RSTATE_IDLE = 2'd0,
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RSTATE_DATA = 2'd1;
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// device caps
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wire [63:0] dev_caps = {16'b0,
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8'(`SM_ENABLED ? `SMEM_LOG_SIZE : 0),
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16'(`NUM_CORES * `NUM_CLUSTERS),
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8'(`NUM_WARPS),
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8'(`NUM_THREADS),
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8'(`IMPLEMENTATION_ID)};
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wire [63:0] isa_caps = {32'(`MISA_EXT),
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2'(`CLOG2(`XLEN)-4),
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30'(`MISA_STD)};
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reg [1:0] wstate;
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reg [ADDR_BITS-1:0] waddr;
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wire [31:0] wmask;
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wire s_axi_aw_fire;
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wire s_axi_w_fire;
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reg [1:0] rstate;
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reg [31:0] rdata;
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wire [ADDR_BITS-1:0] raddr;
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wire s_axi_ar_fire;
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reg ap_reset_r;
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reg ap_start_r;
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reg auto_restart_r;
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reg gie_r;
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reg [1:0] ier_r;
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reg [1:0] isr_r;
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reg [63:0] mem_r [AXI_NUM_BANKS];
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reg [31:0] dcra_r;
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reg [31:0] dcrv_r;
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reg dcr_wr_valid_r;
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`ifdef SCOPE
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reg [63:0] scope_bus_wdata;
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reg [63:0] scope_bus_rdata;
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reg [5:0] scope_bus_ctr;
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reg cmd_scope_reading;
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reg cmd_scope_writing;
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reg scope_bus_out_r;
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always @(posedge clk) begin
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if (reset) begin
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cmd_scope_reading <= 0;
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cmd_scope_writing <= 0;
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scope_bus_ctr <= '0;
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scope_bus_out_r <= 0;
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end else if (clk_en) begin
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if (s_axi_w_fire && waddr == ADDR_SCP_0) begin
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scope_bus_wdata[31:0] <= (s_axi_wdata & wmask) | (scope_bus_wdata[31:0] & ~wmask);
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end
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if (s_axi_w_fire && waddr == ADDR_SCP_1) begin
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scope_bus_wdata[63:32] <= (s_axi_wdata & wmask) | (scope_bus_wdata[63:32] & ~wmask);
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cmd_scope_writing <= 1;
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scope_bus_out_r <= 1;
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scope_bus_ctr <= 63;
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end
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if (scope_bus_in) begin
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cmd_scope_reading <= 1;
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scope_bus_ctr <= 63;
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end
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if (cmd_scope_reading) begin
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scope_bus_rdata <= {scope_bus_rdata[62:0], scope_bus_in};
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scope_bus_ctr <= scope_bus_ctr - 1;
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if (scope_bus_ctr == 0) begin
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cmd_scope_reading <= 0;
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end
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end
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if (cmd_scope_writing) begin
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scope_bus_out_r <= 1'(scope_bus_wdata >> scope_bus_ctr);
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scope_bus_ctr <= scope_bus_ctr - 1;
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if (scope_bus_ctr == 0) begin
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cmd_scope_writing <= 0;
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end
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end
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end
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end
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assign scope_bus_out = scope_bus_out_r;
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`endif
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// AXI Write
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assign s_axi_awready = (wstate == WSTATE_IDLE);
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assign s_axi_wready = (wstate == WSTATE_DATA);
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assign s_axi_bvalid = (wstate == WSTATE_RESP);
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assign s_axi_bresp = 2'b00; // OKAY
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assign s_axi_aw_fire = s_axi_awvalid && s_axi_awready;
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assign s_axi_w_fire = s_axi_wvalid && s_axi_wready;
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for (genvar i = 0; i < 4; ++i) begin
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assign wmask[8 * i +: 8] = {8{s_axi_wstrb[i]}};
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end
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// wstate
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always @(posedge clk) begin
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if (reset) begin
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wstate <= WSTATE_IDLE;
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end else if (clk_en) begin
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case (wstate)
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WSTATE_IDLE: wstate <= s_axi_awvalid ? WSTATE_DATA : WSTATE_IDLE;
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WSTATE_DATA: wstate <= s_axi_wvalid ? WSTATE_RESP : WSTATE_DATA;
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WSTATE_RESP: wstate <= s_axi_bready ? WSTATE_IDLE : WSTATE_RESP;
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default: wstate <= WSTATE_IDLE;
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endcase
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end
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end
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// waddr
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always @(posedge clk) begin
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if (clk_en) begin
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if (s_axi_aw_fire)
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waddr <= s_axi_awaddr[ADDR_BITS-1:0];
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end
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end
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// wdata
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always @(posedge clk) begin
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if (reset) begin
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ap_start_r <= 0;
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ap_reset_r <= 0;
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auto_restart_r <= 0;
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gie_r <= 0;
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ier_r <= '0;
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isr_r <= '0;
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dcra_r <= '0;
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dcrv_r <= '0;
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dcr_wr_valid_r <= 0;
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for (integer i = 0; i < AXI_NUM_BANKS; ++i) begin
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mem_r[i] <= '0;
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end
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end else if (clk_en) begin
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if (ap_ready)
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ap_start_r <= auto_restart_r;
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dcr_wr_valid_r <= 0;
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if (s_axi_w_fire) begin
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case (waddr)
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ADDR_AP_CTRL: begin
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if (s_axi_wstrb[0]) begin
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if (s_axi_wdata[0])
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ap_start_r <= 1;
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if (s_axi_wdata[4])
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ap_reset_r <= 1;
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if (s_axi_wdata[7])
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auto_restart_r <= 1;
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end
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end
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ADDR_GIE: begin
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if (s_axi_wstrb[0])
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gie_r <= s_axi_wdata[0];
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end
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ADDR_IER: begin
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if (s_axi_wstrb[0])
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ier_r <= s_axi_wdata[1:0];
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end
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ADDR_ISR: begin
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if (s_axi_wstrb[0])
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isr_r <= isr_r ^ s_axi_wdata[1:0];
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end
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ADDR_DCR_0: begin
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dcra_r <= (s_axi_wdata & wmask) | (dcra_r & ~wmask);
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end
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ADDR_DCR_1: begin
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dcrv_r <= (s_axi_wdata & wmask) | (dcrv_r & ~wmask);
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dcr_wr_valid_r <= 1;
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end
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default: begin
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for (integer i = 0; i < AXI_NUM_BANKS; ++i) begin
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if (waddr == (ADDR_MEM_0 + i * 12)) begin
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mem_r[i][31:0] <= (s_axi_wdata & wmask) | (mem_r[i][31:0] & ~wmask);
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end
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if (waddr == (ADDR_MEM_1 + i * 12)) begin
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mem_r[i][63:32] <= (s_axi_wdata & wmask) | (mem_r[i][63:32] & ~wmask);
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end
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end
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end
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endcase
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if (ier_r[0] & ap_done)
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isr_r[0] <= 1'b1;
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if (ier_r[1] & ap_ready)
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isr_r[1] <= 1'b1;
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end
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end
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end
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// AXI Read
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assign s_axi_arready = (rstate == RSTATE_IDLE);
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assign s_axi_rvalid = (rstate == RSTATE_DATA);
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assign s_axi_rdata = rdata;
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assign s_axi_rresp = 2'b00; // OKAY
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assign s_axi_ar_fire = s_axi_arvalid && s_axi_arready;
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assign raddr = s_axi_araddr[ADDR_BITS-1:0];
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// rstate
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always @(posedge clk) begin
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if (reset) begin
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rstate <= RSTATE_IDLE;
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end else if (clk_en) begin
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case (rstate)
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RSTATE_IDLE: rstate <= s_axi_arvalid ? RSTATE_DATA : RSTATE_IDLE;
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RSTATE_DATA: rstate <= (s_axi_rready & s_axi_rvalid) ? RSTATE_IDLE : RSTATE_DATA;
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default: rstate <= RSTATE_IDLE;
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endcase
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end
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end
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// rdata
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always @(posedge clk) begin
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if (clk_en) begin
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if (s_axi_ar_fire) begin
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rdata <= '0;
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case (raddr)
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ADDR_AP_CTRL: begin
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rdata[0] <= ap_start_r;
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rdata[1] <= ap_done;
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rdata[2] <= ap_idle;
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rdata[3] <= ap_ready;
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rdata[7] <= auto_restart_r;
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end
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ADDR_GIE: begin
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rdata <= 32'(gie_r);
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end
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ADDR_IER: begin
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rdata <= 32'(ier_r);
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end
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ADDR_ISR: begin
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rdata <= 32'(isr_r);
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end
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ADDR_DEV_0: begin
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rdata <= dev_caps[31:0];
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end
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ADDR_DEV_1: begin
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rdata <= dev_caps[63:32];
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end
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ADDR_ISA_0: begin
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rdata <= isa_caps[31:0];
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end
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ADDR_ISA_1: begin
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rdata <= isa_caps[63:32];
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end
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`ifdef SCOPE
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ADDR_SCP_0: begin
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rdata <= scope_bus_rdata[31:0];
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end
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ADDR_SCP_1: begin
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rdata <= scope_bus_rdata[63:32];
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end
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`endif
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default:;
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endcase
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end
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end
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end
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assign ap_reset = ap_reset_r;
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assign ap_start = ap_start_r;
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assign interrupt = gie_r & (| isr_r);
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assign mem_base = mem_r;
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assign dcr_wr_valid = dcr_wr_valid_r;
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assign dcr_wr_addr = `VX_DCR_ADDR_WIDTH'(dcra_r);
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assign dcr_wr_data = `VX_DCR_DATA_WIDTH'(dcrv_r);
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endmodule
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412
hw/rtl/afu/xrt/VX_afu_wrap.sv
Normal file
412
hw/rtl/afu/xrt/VX_afu_wrap.sv
Normal file
@@ -0,0 +1,412 @@
|
||||
// Copyright © 2019-2023
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
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// http://www.apache.org/licenses/LICENSE-2.0
|
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//
|
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// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
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`include "vortex_afu.vh"
|
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module VX_afu_wrap #(
|
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parameter C_S_AXI_CTRL_ADDR_WIDTH = 8,
|
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parameter C_S_AXI_CTRL_DATA_WIDTH = 32,
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parameter C_M_AXI_MEM_ID_WIDTH = 16,
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parameter C_M_AXI_MEM_ADDR_WIDTH = 32,
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parameter C_M_AXI_MEM_DATA_WIDTH = 512
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) (
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// System signals
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input wire ap_clk,
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input wire ap_rst_n,
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// AXI4 master interface
|
||||
`REPEAT (`M_AXI_MEM_NUM_BANKS, GEN_AXI_MEM, REPEAT_COMMA),
|
||||
|
||||
// AXI4-Lite slave interface
|
||||
input wire s_axi_ctrl_awvalid,
|
||||
output wire s_axi_ctrl_awready,
|
||||
input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr,
|
||||
input wire s_axi_ctrl_wvalid,
|
||||
output wire s_axi_ctrl_wready,
|
||||
input wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata,
|
||||
input wire [C_S_AXI_CTRL_DATA_WIDTH/8-1:0] s_axi_ctrl_wstrb,
|
||||
input wire s_axi_ctrl_arvalid,
|
||||
output wire s_axi_ctrl_arready,
|
||||
input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr,
|
||||
output wire s_axi_ctrl_rvalid,
|
||||
input wire s_axi_ctrl_rready,
|
||||
output wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata,
|
||||
output wire [1:0] s_axi_ctrl_rresp,
|
||||
output wire s_axi_ctrl_bvalid,
|
||||
input wire s_axi_ctrl_bready,
|
||||
output wire [1:0] s_axi_ctrl_bresp,
|
||||
|
||||
output wire interrupt
|
||||
);
|
||||
localparam C_M_AXI_MEM_NUM_BANKS = `M_AXI_MEM_NUM_BANKS;
|
||||
|
||||
localparam STATE_IDLE = 0;
|
||||
localparam STATE_RUN = 1;
|
||||
|
||||
wire m_axi_mem_awvalid_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_awready_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_awaddr_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_awid_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [7:0] m_axi_mem_awlen_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_wvalid_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_wready_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [C_M_AXI_MEM_DATA_WIDTH-1:0] m_axi_mem_wdata_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [C_M_AXI_MEM_DATA_WIDTH/8-1:0] m_axi_mem_wstrb_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_wlast_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_bvalid_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_bready_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_bid_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [1:0] m_axi_mem_bresp_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_arvalid_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_arready_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_araddr_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_arid_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [7:0] m_axi_mem_arlen_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_rvalid_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_rready_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [C_M_AXI_MEM_DATA_WIDTH-1:0] m_axi_mem_rdata_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire m_axi_mem_rlast_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_rid_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [1:0] m_axi_mem_rresp_a [C_M_AXI_MEM_NUM_BANKS];
|
||||
|
||||
// convert memory interface to array
|
||||
`REPEAT (`M_AXI_MEM_NUM_BANKS, AXI_MEM_TO_ARRAY, REPEAT_SEMICOLON);
|
||||
|
||||
wire clk = ap_clk;
|
||||
wire reset = ~ap_rst_n;
|
||||
|
||||
reg [`CLOG2(`RESET_DELAY+1)-1:0] vx_reset_ctr;
|
||||
reg [15:0] vx_pending_writes;
|
||||
reg vx_busy_wait;
|
||||
reg vx_running;
|
||||
|
||||
wire vx_busy;
|
||||
|
||||
wire [63:0] mem_base [C_M_AXI_MEM_NUM_BANKS];
|
||||
|
||||
wire dcr_wr_valid;
|
||||
wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr;
|
||||
wire [`VX_DCR_DATA_WIDTH-1:0] dcr_wr_data;
|
||||
|
||||
reg state;
|
||||
|
||||
wire ap_reset;
|
||||
wire ap_start;
|
||||
wire ap_idle = ~vx_running;
|
||||
wire ap_done = ~(state == STATE_RUN || vx_pending_writes != 0);
|
||||
wire ap_ready = 1'b1;
|
||||
|
||||
`ifdef SCOPE
|
||||
wire scope_bus_in;
|
||||
wire scope_bus_out;
|
||||
wire scope_reset = reset;
|
||||
`endif
|
||||
|
||||
always @(posedge ap_clk) begin
|
||||
if (reset || ap_reset) begin
|
||||
state <= STATE_IDLE;
|
||||
vx_busy_wait <= 0;
|
||||
vx_running <= 0;
|
||||
end else begin
|
||||
case (state)
|
||||
STATE_IDLE: begin
|
||||
if (ap_start) begin
|
||||
`ifdef DBG_TRACE_AFU
|
||||
`TRACE(2, ("%d: STATE RUN\n", $time));
|
||||
`endif
|
||||
state <= STATE_RUN;
|
||||
vx_running <= 0;
|
||||
end
|
||||
end
|
||||
STATE_RUN: begin
|
||||
if (vx_running) begin
|
||||
if (vx_busy_wait) begin
|
||||
// wait until processor goes busy
|
||||
if (vx_busy) begin
|
||||
vx_busy_wait <= 0;
|
||||
end
|
||||
end else begin
|
||||
// wait until the processor is not busy
|
||||
if (~vx_busy) begin
|
||||
state <= STATE_IDLE;
|
||||
`ifdef DBG_TRACE_AFU
|
||||
`TRACE(2, ("%d: AFU: End execution\n", $time));
|
||||
`TRACE(2, ("%d: STATE IDLE\n", $time));
|
||||
`endif
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
// wait until the reset sequence is complete
|
||||
if (vx_reset_ctr == (`RESET_DELAY-1)) begin
|
||||
`ifdef DBG_TRACE_AFU
|
||||
`TRACE(2, ("%d: AFU: Begin execution\n", $time));
|
||||
`endif
|
||||
vx_running <= 1;
|
||||
vx_busy_wait <= 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
reg m_axi_mem_wfire;
|
||||
reg m_axi_mem_bfire;
|
||||
|
||||
always @(*) begin
|
||||
m_axi_mem_wfire = 0;
|
||||
m_axi_mem_bfire = 0;
|
||||
for (integer i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin
|
||||
m_axi_mem_wfire |= m_axi_mem_wvalid_a[i] && m_axi_mem_wready_a[i];
|
||||
m_axi_mem_bfire |= m_axi_mem_bvalid_a[i] && m_axi_mem_bready_a[i];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge ap_clk) begin
|
||||
if (reset || ap_reset) begin
|
||||
vx_pending_writes <= '0;
|
||||
end else begin
|
||||
if (m_axi_mem_wfire && ~m_axi_mem_bfire)
|
||||
vx_pending_writes <= vx_pending_writes + 1;
|
||||
if (~m_axi_mem_wfire && m_axi_mem_bfire)
|
||||
vx_pending_writes <= vx_pending_writes - 1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge ap_clk) begin
|
||||
if (state == STATE_RUN) begin
|
||||
vx_reset_ctr <= vx_reset_ctr + 1;
|
||||
end else begin
|
||||
vx_reset_ctr <= '0;
|
||||
end
|
||||
end
|
||||
|
||||
VX_afu_ctrl #(
|
||||
.AXI_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH),
|
||||
.AXI_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH),
|
||||
.AXI_NUM_BANKS (C_M_AXI_MEM_NUM_BANKS)
|
||||
) afu_ctrl (
|
||||
.clk (ap_clk),
|
||||
.reset (reset || ap_reset),
|
||||
.clk_en (1'b1),
|
||||
|
||||
.s_axi_awvalid (s_axi_ctrl_awvalid),
|
||||
.s_axi_awready (s_axi_ctrl_awready),
|
||||
.s_axi_awaddr (s_axi_ctrl_awaddr),
|
||||
.s_axi_wvalid (s_axi_ctrl_wvalid),
|
||||
.s_axi_wready (s_axi_ctrl_wready),
|
||||
.s_axi_wdata (s_axi_ctrl_wdata),
|
||||
.s_axi_wstrb (s_axi_ctrl_wstrb),
|
||||
.s_axi_arvalid (s_axi_ctrl_arvalid),
|
||||
.s_axi_arready (s_axi_ctrl_arready),
|
||||
.s_axi_araddr (s_axi_ctrl_araddr),
|
||||
.s_axi_rvalid (s_axi_ctrl_rvalid),
|
||||
.s_axi_rready (s_axi_ctrl_rready),
|
||||
.s_axi_rdata (s_axi_ctrl_rdata),
|
||||
.s_axi_rresp (s_axi_ctrl_rresp),
|
||||
.s_axi_bvalid (s_axi_ctrl_bvalid),
|
||||
.s_axi_bready (s_axi_ctrl_bready),
|
||||
.s_axi_bresp (s_axi_ctrl_bresp),
|
||||
|
||||
.ap_reset (ap_reset),
|
||||
.ap_start (ap_start),
|
||||
.ap_done (ap_done),
|
||||
.ap_ready (ap_ready),
|
||||
.ap_idle (ap_idle),
|
||||
.interrupt (interrupt),
|
||||
|
||||
`ifdef SCOPE
|
||||
.scope_bus_in (scope_bus_out),
|
||||
.scope_bus_out (scope_bus_in),
|
||||
`endif
|
||||
|
||||
.mem_base (mem_base),
|
||||
|
||||
.dcr_wr_valid (dcr_wr_valid),
|
||||
.dcr_wr_addr (dcr_wr_addr),
|
||||
.dcr_wr_data (dcr_wr_data)
|
||||
);
|
||||
|
||||
wire [`XLEN-1:0] m_axi_mem_awaddr_w [C_M_AXI_MEM_NUM_BANKS];
|
||||
wire [`XLEN-1:0] m_axi_mem_araddr_w [C_M_AXI_MEM_NUM_BANKS];
|
||||
|
||||
for (genvar i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin
|
||||
assign m_axi_mem_awaddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_awaddr_w[i]) + C_M_AXI_MEM_ADDR_WIDTH'(mem_base[i]);
|
||||
assign m_axi_mem_araddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_araddr_w[i]) + C_M_AXI_MEM_ADDR_WIDTH'(mem_base[i]);
|
||||
end
|
||||
|
||||
`SCOPE_IO_SWITCH (2)
|
||||
|
||||
Vortex_axi #(
|
||||
.AXI_DATA_WIDTH (C_M_AXI_MEM_DATA_WIDTH),
|
||||
.AXI_ADDR_WIDTH (`XLEN),
|
||||
.AXI_TID_WIDTH (C_M_AXI_MEM_ID_WIDTH),
|
||||
.AXI_NUM_BANKS (C_M_AXI_MEM_NUM_BANKS)
|
||||
) vortex_axi (
|
||||
`SCOPE_IO_BIND (1)
|
||||
|
||||
.clk (ap_clk),
|
||||
.reset (reset || ap_reset || ~vx_running),
|
||||
|
||||
.m_axi_awvalid (m_axi_mem_awvalid_a),
|
||||
.m_axi_awready (m_axi_mem_awready_a),
|
||||
.m_axi_awaddr (m_axi_mem_awaddr_w),
|
||||
.m_axi_awid (m_axi_mem_awid_a),
|
||||
`UNUSED_PIN (m_axi_awlen),
|
||||
`UNUSED_PIN (m_axi_awsize),
|
||||
`UNUSED_PIN (m_axi_awburst),
|
||||
`UNUSED_PIN (m_axi_awlock),
|
||||
`UNUSED_PIN (m_axi_awcache),
|
||||
`UNUSED_PIN (m_axi_awprot),
|
||||
`UNUSED_PIN (m_axi_awqos),
|
||||
`UNUSED_PIN (m_axi_awregion),
|
||||
|
||||
.m_axi_wvalid (m_axi_mem_wvalid_a),
|
||||
.m_axi_wready (m_axi_mem_wready_a),
|
||||
.m_axi_wdata (m_axi_mem_wdata_a),
|
||||
.m_axi_wstrb (m_axi_mem_wstrb_a),
|
||||
.m_axi_wlast (m_axi_mem_wlast_a),
|
||||
|
||||
.m_axi_bvalid (m_axi_mem_bvalid_a),
|
||||
.m_axi_bready (m_axi_mem_bready_a),
|
||||
.m_axi_bid (m_axi_mem_bid_a),
|
||||
.m_axi_bresp (m_axi_mem_bresp_a),
|
||||
|
||||
.m_axi_arvalid (m_axi_mem_arvalid_a),
|
||||
.m_axi_arready (m_axi_mem_arready_a),
|
||||
.m_axi_araddr (m_axi_mem_araddr_w),
|
||||
.m_axi_arid (m_axi_mem_arid_a),
|
||||
.m_axi_arlen (m_axi_mem_arlen_a),
|
||||
`UNUSED_PIN (m_axi_arsize),
|
||||
`UNUSED_PIN (m_axi_arburst),
|
||||
`UNUSED_PIN (m_axi_arlock),
|
||||
`UNUSED_PIN (m_axi_arcache),
|
||||
`UNUSED_PIN (m_axi_arprot),
|
||||
`UNUSED_PIN (m_axi_arqos),
|
||||
`UNUSED_PIN (m_axi_arregion),
|
||||
|
||||
.m_axi_rvalid (m_axi_mem_rvalid_a),
|
||||
.m_axi_rready (m_axi_mem_rready_a),
|
||||
.m_axi_rdata (m_axi_mem_rdata_a),
|
||||
.m_axi_rlast (m_axi_mem_rlast_a),
|
||||
.m_axi_rid (m_axi_mem_rid_a),
|
||||
.m_axi_rresp (m_axi_mem_rresp_a),
|
||||
|
||||
.dcr_wr_valid (dcr_wr_valid),
|
||||
.dcr_wr_addr (dcr_wr_addr),
|
||||
.dcr_wr_data (dcr_wr_data),
|
||||
|
||||
.busy (vx_busy)
|
||||
);
|
||||
|
||||
// SCOPE //////////////////////////////////////////////////////////////////////
|
||||
|
||||
`ifdef DBG_SCOPE_AFU
|
||||
`ifdef SCOPE
|
||||
`define TRIGGERS { \
|
||||
reset, \
|
||||
ap_start, \
|
||||
ap_done, \
|
||||
ap_idle, \
|
||||
interrupt, \
|
||||
vx_busy_wait, \
|
||||
vx_busy, \
|
||||
vx_running \
|
||||
}
|
||||
|
||||
`define PROBES { \
|
||||
vx_pending_writes \
|
||||
}
|
||||
|
||||
VX_scope_tap #(
|
||||
.SCOPE_ID (0),
|
||||
.TRIGGERW ($bits(`TRIGGERS)),
|
||||
.PROBEW ($bits(`PROBES))
|
||||
) scope_tap (
|
||||
.clk(clk),
|
||||
.reset(scope_reset_w[0]),
|
||||
.start(1'b0),
|
||||
.stop(1'b0),
|
||||
.triggers(`TRIGGERS),
|
||||
.probes(`PROBES),
|
||||
.bus_in(scope_bus_in_w[0]),
|
||||
.bus_out(scope_bus_out_w[0])
|
||||
);
|
||||
`endif
|
||||
`ifdef CHIPSCOPE
|
||||
ila_afu ila_afu_inst (
|
||||
.clk (ap_clk),
|
||||
.probe0 ({
|
||||
ap_start,
|
||||
ap_done,
|
||||
ap_idle,
|
||||
interrupt
|
||||
}),
|
||||
.probe1 ({
|
||||
vx_pending_writes,
|
||||
vx_busy_wait,
|
||||
vx_busy,
|
||||
vx_running
|
||||
})
|
||||
);
|
||||
`endif
|
||||
`else
|
||||
`SCOPE_IO_UNUSED_W(0)
|
||||
`endif
|
||||
|
||||
`ifdef SIMULATION
|
||||
`ifndef VERILATOR
|
||||
// disable assertions until full reset
|
||||
reg [`CLOG2(`RESET_DELAY+1)-1:0] assert_delay_ctr;
|
||||
reg assert_enabled;
|
||||
initial begin
|
||||
$assertoff(0, vortex_axi);
|
||||
end
|
||||
always @(posedge ap_clk) begin
|
||||
if (reset) begin
|
||||
assert_delay_ctr <= '0;
|
||||
assert_enabled <= 0;
|
||||
end else begin
|
||||
if (~assert_enabled) begin
|
||||
if (assert_delay_ctr == (`RESET_DELAY-1)) begin
|
||||
assert_enabled <= 1;
|
||||
$asserton(0, vortex_axi); // enable assertions
|
||||
end else begin
|
||||
assert_delay_ctr <= assert_delay_ctr + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
`endif
|
||||
`endif
|
||||
|
||||
`ifdef DBG_TRACE_AFU
|
||||
always @(posedge ap_clk) begin
|
||||
for (integer i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin
|
||||
if (m_axi_mem_awvalid_a[i] && m_axi_mem_awready_a[i]) begin
|
||||
`TRACE(2, ("%d: AFU Wr Req [%0d]: addr=0x%0h, tag=0x%0h\n", $time, i, m_axi_mem_awaddr_a[i], m_axi_mem_awid_a[i]));
|
||||
end
|
||||
if (m_axi_mem_wvalid_a[i] && m_axi_mem_wready_a[i]) begin
|
||||
`TRACE(2, ("%d: AFU Wr Req [%0d]: data=0x%0h\n", $time, i, m_axi_mem_wdata_a[i]));
|
||||
end
|
||||
if (m_axi_mem_arvalid_a[i] && m_axi_mem_arready_a[i]) begin
|
||||
`TRACE(2, ("%d: AFU Rd Req [%0d]: addr=0x%0h, tag=0x%0h\n", $time, i, m_axi_mem_araddr_a[i], m_axi_mem_arid_a[i]));
|
||||
end
|
||||
if (m_axi_mem_rvalid_a[i] && m_axi_mem_rready_a[i]) begin
|
||||
`TRACE(2, ("%d: AVS Rd Rsp [%0d]: data=0x%0h, tag=0x%0h\n", $time, i, m_axi_mem_rdata_a[i], m_axi_mem_rid_a[i]));
|
||||
end
|
||||
end
|
||||
end
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
85
hw/rtl/afu/xrt/vortex_afu.v
Normal file
85
hw/rtl/afu/xrt/vortex_afu.v
Normal file
@@ -0,0 +1,85 @@
|
||||
// Copyright © 2019-2023
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
`include "vortex_afu.vh"
|
||||
|
||||
module vortex_afu #(
|
||||
parameter C_S_AXI_CTRL_ADDR_WIDTH = 8,
|
||||
parameter C_S_AXI_CTRL_DATA_WIDTH = 32,
|
||||
parameter C_M_AXI_MEM_ID_WIDTH = `M_AXI_MEM_ID_WIDTH,
|
||||
parameter C_M_AXI_MEM_ADDR_WIDTH = 64,
|
||||
parameter C_M_AXI_MEM_DATA_WIDTH = `VX_MEM_DATA_WIDTH
|
||||
) (
|
||||
// System signals
|
||||
input wire ap_clk,
|
||||
input wire ap_rst_n,
|
||||
|
||||
// AXI4 master interface
|
||||
`REPEAT (`M_AXI_MEM_NUM_BANKS, GEN_AXI_MEM, REPEAT_COMMA),
|
||||
|
||||
// AXI4-Lite slave interface
|
||||
input wire s_axi_ctrl_awvalid,
|
||||
output wire s_axi_ctrl_awready,
|
||||
input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr,
|
||||
input wire s_axi_ctrl_wvalid,
|
||||
output wire s_axi_ctrl_wready,
|
||||
input wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata,
|
||||
input wire [C_S_AXI_CTRL_DATA_WIDTH/8-1:0] s_axi_ctrl_wstrb,
|
||||
input wire s_axi_ctrl_arvalid,
|
||||
output wire s_axi_ctrl_arready,
|
||||
input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr,
|
||||
output wire s_axi_ctrl_rvalid,
|
||||
input wire s_axi_ctrl_rready,
|
||||
output wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata,
|
||||
output wire [1:0] s_axi_ctrl_rresp,
|
||||
output wire s_axi_ctrl_bvalid,
|
||||
input wire s_axi_ctrl_bready,
|
||||
output wire [1:0] s_axi_ctrl_bresp,
|
||||
|
||||
output wire interrupt
|
||||
);
|
||||
|
||||
VX_afu_wrap #(
|
||||
.C_S_AXI_CTRL_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH),
|
||||
.C_S_AXI_CTRL_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH),
|
||||
.C_M_AXI_MEM_ID_WIDTH (C_M_AXI_MEM_ID_WIDTH),
|
||||
.C_M_AXI_MEM_ADDR_WIDTH (C_M_AXI_MEM_ADDR_WIDTH),
|
||||
.C_M_AXI_MEM_DATA_WIDTH (C_M_AXI_MEM_DATA_WIDTH)
|
||||
) afu_wrap (
|
||||
.ap_clk (ap_clk),
|
||||
.ap_rst_n (ap_rst_n),
|
||||
|
||||
`REPEAT (`M_AXI_MEM_NUM_BANKS, AXI_MEM_ARGS, REPEAT_COMMA),
|
||||
|
||||
.s_axi_ctrl_awvalid (s_axi_ctrl_awvalid),
|
||||
.s_axi_ctrl_awready (s_axi_ctrl_awready),
|
||||
.s_axi_ctrl_awaddr (s_axi_ctrl_awaddr),
|
||||
.s_axi_ctrl_wvalid (s_axi_ctrl_wvalid),
|
||||
.s_axi_ctrl_wready (s_axi_ctrl_wready),
|
||||
.s_axi_ctrl_wdata (s_axi_ctrl_wdata),
|
||||
.s_axi_ctrl_wstrb (s_axi_ctrl_wstrb),
|
||||
.s_axi_ctrl_arvalid (s_axi_ctrl_arvalid),
|
||||
.s_axi_ctrl_arready (s_axi_ctrl_arready),
|
||||
.s_axi_ctrl_araddr (s_axi_ctrl_araddr),
|
||||
.s_axi_ctrl_rvalid (s_axi_ctrl_rvalid),
|
||||
.s_axi_ctrl_rready (s_axi_ctrl_rready),
|
||||
.s_axi_ctrl_rdata (s_axi_ctrl_rdata),
|
||||
.s_axi_ctrl_rresp (s_axi_ctrl_rresp),
|
||||
.s_axi_ctrl_bvalid (s_axi_ctrl_bvalid),
|
||||
.s_axi_ctrl_bready (s_axi_ctrl_bready),
|
||||
.s_axi_ctrl_bresp (s_axi_ctrl_bresp),
|
||||
|
||||
.interrupt (interrupt)
|
||||
);
|
||||
|
||||
endmodule
|
||||
108
hw/rtl/afu/xrt/vortex_afu.vh
Normal file
108
hw/rtl/afu/xrt/vortex_afu.vh
Normal file
@@ -0,0 +1,108 @@
|
||||
// Copyright © 2019-2023
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
`ifndef VORTEX_AFU_VH
|
||||
`define VORTEX_AFU_VH
|
||||
|
||||
`ifndef M_AXI_MEM_NUM_BANKS
|
||||
`define M_AXI_MEM_NUM_BANKS 1
|
||||
`endif
|
||||
|
||||
`ifndef M_AXI_MEM_ID_WIDTH
|
||||
`define M_AXI_MEM_ID_WIDTH 32
|
||||
`endif
|
||||
|
||||
`define GEN_AXI_MEM(i) \
|
||||
output wire m_axi_mem_``i``_awvalid, \
|
||||
input wire m_axi_mem_``i``_awready, \
|
||||
output wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_``i``_awaddr, \
|
||||
output wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_``i``_awid, \
|
||||
output wire [7:0] m_axi_mem_``i``_awlen, \
|
||||
output wire m_axi_mem_``i``_wvalid, \
|
||||
input wire m_axi_mem_``i``_wready, \
|
||||
output wire [C_M_AXI_MEM_DATA_WIDTH-1:0] m_axi_mem_``i``_wdata, \
|
||||
output wire [C_M_AXI_MEM_DATA_WIDTH/8-1:0] m_axi_mem_``i``_wstrb, \
|
||||
output wire m_axi_mem_``i``_wlast, \
|
||||
output wire m_axi_mem_``i``_arvalid, \
|
||||
input wire m_axi_mem_``i``_arready, \
|
||||
output wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_``i``_araddr, \
|
||||
output wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_``i``_arid, \
|
||||
output wire [7:0] m_axi_mem_``i``_arlen, \
|
||||
input wire m_axi_mem_``i``_rvalid, \
|
||||
output wire m_axi_mem_``i``_rready, \
|
||||
input wire [C_M_AXI_MEM_DATA_WIDTH-1:0] m_axi_mem_``i``_rdata, \
|
||||
input wire m_axi_mem_``i``_rlast, \
|
||||
input wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_``i``_rid, \
|
||||
input wire [1:0] m_axi_mem_``i``_rresp, \
|
||||
input wire m_axi_mem_``i``_bvalid, \
|
||||
output wire m_axi_mem_``i``_bready, \
|
||||
input wire [1:0] m_axi_mem_``i``_bresp, \
|
||||
input wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_``i``_bid
|
||||
|
||||
`define AXI_MEM_ARGS(i) \
|
||||
.m_axi_mem_``i``_awvalid(m_axi_mem_``i``_awvalid), \
|
||||
.m_axi_mem_``i``_awready(m_axi_mem_``i``_awready), \
|
||||
.m_axi_mem_``i``_awaddr(m_axi_mem_``i``_awaddr), \
|
||||
.m_axi_mem_``i``_awid(m_axi_mem_``i``_awid), \
|
||||
.m_axi_mem_``i``_awlen(m_axi_mem_``i``_awlen), \
|
||||
.m_axi_mem_``i``_wvalid(m_axi_mem_``i``_wvalid), \
|
||||
.m_axi_mem_``i``_wready(m_axi_mem_``i``_wready), \
|
||||
.m_axi_mem_``i``_wdata(m_axi_mem_``i``_wdata), \
|
||||
.m_axi_mem_``i``_wstrb(m_axi_mem_``i``_wstrb), \
|
||||
.m_axi_mem_``i``_wlast(m_axi_mem_``i``_wlast), \
|
||||
.m_axi_mem_``i``_arvalid(m_axi_mem_``i``_arvalid), \
|
||||
.m_axi_mem_``i``_arready(m_axi_mem_``i``_arready), \
|
||||
.m_axi_mem_``i``_araddr(m_axi_mem_``i``_araddr), \
|
||||
.m_axi_mem_``i``_arid(m_axi_mem_``i``_arid), \
|
||||
.m_axi_mem_``i``_arlen(m_axi_mem_``i``_arlen), \
|
||||
.m_axi_mem_``i``_rvalid(m_axi_mem_``i``_rvalid), \
|
||||
.m_axi_mem_``i``_rready(m_axi_mem_``i``_rready), \
|
||||
.m_axi_mem_``i``_rdata(m_axi_mem_``i``_rdata), \
|
||||
.m_axi_mem_``i``_rlast(m_axi_mem_``i``_rlast), \
|
||||
.m_axi_mem_``i``_rid(m_axi_mem_``i``_rid), \
|
||||
.m_axi_mem_``i``_rresp(m_axi_mem_``i``_rresp), \
|
||||
.m_axi_mem_``i``_bvalid(m_axi_mem_``i``_bvalid), \
|
||||
.m_axi_mem_``i``_bready(m_axi_mem_``i``_bready), \
|
||||
.m_axi_mem_``i``_bresp(m_axi_mem_``i``_bresp), \
|
||||
.m_axi_mem_``i``_bid(m_axi_mem_``i``_bid)
|
||||
|
||||
`define AXI_MEM_TO_ARRAY(i) \
|
||||
assign m_axi_mem_``i``_awvalid = m_axi_mem_awvalid_a[i]; \
|
||||
assign m_axi_mem_awready_a[i] = m_axi_mem_``i``_awready; \
|
||||
assign m_axi_mem_``i``_awaddr = m_axi_mem_awaddr_a[i]; \
|
||||
assign m_axi_mem_``i``_awid = m_axi_mem_awid_a[i]; \
|
||||
assign m_axi_mem_``i``_awlen = m_axi_mem_awlen_a[i]; \
|
||||
assign m_axi_mem_``i``_wvalid = m_axi_mem_wvalid_a[i]; \
|
||||
assign m_axi_mem_wready_a[i] = m_axi_mem_``i``_wready; \
|
||||
assign m_axi_mem_``i``_wdata = m_axi_mem_wdata_a[i]; \
|
||||
assign m_axi_mem_``i``_wstrb = m_axi_mem_wstrb_a[i]; \
|
||||
assign m_axi_mem_``i``_wlast = m_axi_mem_wlast_a[i]; \
|
||||
assign m_axi_mem_``i``_arvalid = m_axi_mem_arvalid_a[i]; \
|
||||
assign m_axi_mem_arready_a[i] = m_axi_mem_``i``_arready; \
|
||||
assign m_axi_mem_``i``_araddr = m_axi_mem_araddr_a[i]; \
|
||||
assign m_axi_mem_``i``_arid = m_axi_mem_arid_a[i]; \
|
||||
assign m_axi_mem_``i``_arlen = m_axi_mem_arlen_a[i]; \
|
||||
assign m_axi_mem_rvalid_a[i] = m_axi_mem_``i``_rvalid; \
|
||||
assign m_axi_mem_``i``_rready = m_axi_mem_rready_a[i]; \
|
||||
assign m_axi_mem_rdata_a[i] = m_axi_mem_``i``_rdata; \
|
||||
assign m_axi_mem_rlast_a[i] = m_axi_mem_``i``_rlast; \
|
||||
assign m_axi_mem_rid_a[i] = m_axi_mem_``i``_rid; \
|
||||
assign m_axi_mem_rresp_a[i] = m_axi_mem_``i``_rresp; \
|
||||
assign m_axi_mem_bvalid_a[i] = m_axi_mem_``i``_bvalid; \
|
||||
assign m_axi_mem_``i``_bready = m_axi_mem_bready_a[i]; \
|
||||
assign m_axi_mem_bresp_a[i] = m_axi_mem_``i``_bresp; \
|
||||
assign m_axi_mem_bid_a[i] = m_axi_mem_``i``_bid
|
||||
|
||||
`include "VX_define.vh"
|
||||
|
||||
`endif // VORTEX_AFU_VH
|
||||
Reference in New Issue
Block a user