Vortex 2.0 changes:
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
This commit is contained in:
Blaise Tine
327
hw/rtl/Vortex.sv
327
hw/rtl/Vortex.sv
@@ -1,7 +1,20 @@
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// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module Vortex (
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`SCOPE_IO_Vortex
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module Vortex import VX_gpu_pkg::*; (
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`SCOPE_IO_DECL
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// Clock
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input wire clk,
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@@ -22,204 +35,186 @@ module Vortex (
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input wire [`VX_MEM_TAG_WIDTH-1:0] mem_rsp_tag,
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output wire mem_rsp_ready,
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// DCR write request
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input wire dcr_wr_valid,
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input wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr,
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input wire [`VX_DCR_DATA_WIDTH-1:0] dcr_wr_data,
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// Status
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output wire busy
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);
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`STATIC_ASSERT((`L3_ENABLE == 0 || `NUM_CLUSTERS > 1), ("invalid parameter"))
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wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_valid;
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wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_rw;
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wire [`NUM_CLUSTERS-1:0][`L2_MEM_BYTEEN_WIDTH-1:0] per_cluster_mem_req_byteen;
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wire [`NUM_CLUSTERS-1:0][`L2_MEM_ADDR_WIDTH-1:0] per_cluster_mem_req_addr;
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wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_req_data;
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wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0] per_cluster_mem_req_tag;
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wire [`NUM_CLUSTERS-1:0] per_cluster_mem_req_ready;
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`ifdef PERF_ENABLE
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VX_mem_perf_if mem_perf_if();
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cache_perf_t perf_l3cache;
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mem_perf_t mem_perf;
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wire [`NUM_CLUSTERS-1:0] per_cluster_mem_rsp_valid;
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wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_rsp_data;
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wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0] per_cluster_mem_rsp_tag;
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wire [`NUM_CLUSTERS-1:0] per_cluster_mem_rsp_ready;
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assign mem_perf_if.icache = 'x;
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assign mem_perf_if.dcache = 'x;
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assign mem_perf_if.l2cache = 'x;
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assign mem_perf_if.l3cache = perf_l3cache;
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assign mem_perf_if.smem = 'x;
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assign mem_perf_if.mem = mem_perf;
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`endif
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wire [`NUM_CLUSTERS-1:0] per_cluster_busy;
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VX_mem_bus_if #(
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.DATA_SIZE (`L2_LINE_SIZE),
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.TAG_WIDTH (L2_MEM_TAG_WIDTH)
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) per_cluster_mem_bus_if[`NUM_CLUSTERS]();
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for (genvar i = 0; i < `NUM_CLUSTERS; i++) begin
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VX_mem_bus_if #(
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.DATA_SIZE (`L3_LINE_SIZE),
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.TAG_WIDTH (L3_MEM_TAG_WIDTH)
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) mem_bus_if();
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`RESET_RELAY (cluster_reset);
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`RESET_RELAY (l3_reset, reset);
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VX_cluster #(
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.CLUSTER_ID(i)
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) cluster (
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`SCOPE_BIND_Vortex_cluster(i)
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VX_cache_wrap #(
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.INSTANCE_ID ("l3cache"),
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.CACHE_SIZE (`L3_CACHE_SIZE),
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.LINE_SIZE (`L3_LINE_SIZE),
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.NUM_BANKS (`L3_NUM_BANKS),
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.NUM_WAYS (`L3_NUM_WAYS),
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.WORD_SIZE (L3_WORD_SIZE),
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.NUM_REQS (L3_NUM_REQS),
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.CRSQ_SIZE (`L3_CRSQ_SIZE),
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.MSHR_SIZE (`L3_MSHR_SIZE),
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.MRSQ_SIZE (`L3_MRSQ_SIZE),
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.MREQ_SIZE (`L3_MREQ_SIZE),
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.TAG_WIDTH (L2_MEM_TAG_WIDTH),
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.WRITE_ENABLE (1),
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.UUID_WIDTH (`UUID_WIDTH),
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.CORE_OUT_REG (2),
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.MEM_OUT_REG (2),
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.NC_ENABLE (1),
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.PASSTHRU (!`L3_ENABLED)
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) l3cache (
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.clk (clk),
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.reset (l3_reset),
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.clk (clk),
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.reset (cluster_reset),
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.mem_req_valid (per_cluster_mem_req_valid [i]),
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.mem_req_rw (per_cluster_mem_req_rw [i]),
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.mem_req_byteen (per_cluster_mem_req_byteen[i]),
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.mem_req_addr (per_cluster_mem_req_addr [i]),
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.mem_req_data (per_cluster_mem_req_data [i]),
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.mem_req_tag (per_cluster_mem_req_tag [i]),
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.mem_req_ready (per_cluster_mem_req_ready [i]),
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.mem_rsp_valid (per_cluster_mem_rsp_valid [i]),
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.mem_rsp_data (per_cluster_mem_rsp_data [i]),
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.mem_rsp_tag (per_cluster_mem_rsp_tag [i]),
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.mem_rsp_ready (per_cluster_mem_rsp_ready [i]),
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.busy (per_cluster_busy [i])
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);
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end
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assign busy = (| per_cluster_busy);
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if (`L3_ENABLE) begin
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`ifdef PERF_ENABLE
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VX_perf_cache_if perf_l3cache_if();
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.cache_perf (perf_l3cache),
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`endif
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`RESET_RELAY (l3_reset);
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.core_bus_if (per_cluster_mem_bus_if),
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.mem_bus_if (mem_bus_if)
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);
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assign mem_req_valid = mem_bus_if.req_valid;
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assign mem_req_rw = mem_bus_if.req_data.rw;
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assign mem_req_byteen= mem_bus_if.req_data.byteen;
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assign mem_req_addr = mem_bus_if.req_data.addr;
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assign mem_req_data = mem_bus_if.req_data.data;
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assign mem_req_tag = mem_bus_if.req_data.tag;
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assign mem_bus_if.req_ready = mem_req_ready;
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assign mem_bus_if.rsp_valid = mem_rsp_valid;
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assign mem_bus_if.rsp_data.data = mem_rsp_data;
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assign mem_bus_if.rsp_data.tag = mem_rsp_tag;
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assign mem_rsp_ready = mem_bus_if.rsp_ready;
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wire mem_req_fire = mem_req_valid && mem_req_ready;
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wire mem_rsp_fire = mem_rsp_valid && mem_rsp_ready;
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`UNUSED_VAR (mem_req_fire)
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`UNUSED_VAR (mem_rsp_fire)
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wire sim_ebreak /* verilator public */;
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wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value /* verilator public */;
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wire [`NUM_CLUSTERS-1:0] per_cluster_sim_ebreak;
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wire [`NUM_CLUSTERS-1:0][`NUM_REGS-1:0][`XLEN-1:0] per_cluster_sim_wb_value;
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assign sim_ebreak = per_cluster_sim_ebreak[0];
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assign sim_wb_value = per_cluster_sim_wb_value[0];
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`UNUSED_VAR (per_cluster_sim_ebreak)
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`UNUSED_VAR (per_cluster_sim_wb_value)
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VX_dcr_bus_if dcr_bus_if();
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assign dcr_bus_if.write_valid = dcr_wr_valid;
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assign dcr_bus_if.write_addr = dcr_wr_addr;
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assign dcr_bus_if.write_data = dcr_wr_data;
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wire [`NUM_CLUSTERS-1:0] per_cluster_busy;
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`SCOPE_IO_SWITCH (`NUM_CLUSTERS)
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// Generate all clusters
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for (genvar i = 0; i < `NUM_CLUSTERS; ++i) begin
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`RESET_RELAY (cluster_reset, reset);
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`BUFFER_DCR_BUS_IF (cluster_dcr_bus_if, dcr_bus_if, (`NUM_CLUSTERS > 1));
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VX_cluster #(
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.CLUSTER_ID (i)
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) cluster (
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`SCOPE_IO_BIND (i)
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VX_cache #(
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.CACHE_ID (`L3_CACHE_ID),
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.CACHE_SIZE (`L3_CACHE_SIZE),
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.CACHE_LINE_SIZE (`L3_CACHE_LINE_SIZE),
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.NUM_BANKS (`L3_NUM_BANKS),
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.NUM_PORTS (`L3_NUM_PORTS),
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.WORD_SIZE (`L3_WORD_SIZE),
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.NUM_REQS (`L3_NUM_REQS),
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.CREQ_SIZE (`L3_CREQ_SIZE),
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.CRSQ_SIZE (`L3_CRSQ_SIZE),
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.MSHR_SIZE (`L3_MSHR_SIZE),
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.MRSQ_SIZE (`L3_MRSQ_SIZE),
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.MREQ_SIZE (`L3_MREQ_SIZE),
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.WRITE_ENABLE (1),
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.CORE_TAG_WIDTH (`L2_MEM_TAG_WIDTH),
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.CORE_TAG_ID_BITS (0),
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.MEM_TAG_WIDTH (`L3_MEM_TAG_WIDTH),
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.NC_ENABLE (1)
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) l3cache (
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`SCOPE_BIND_Vortex_l3cache
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.clk (clk),
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.reset (l3_reset),
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.reset (cluster_reset),
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`ifdef PERF_ENABLE
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.perf_cache_if (perf_l3cache_if),
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.mem_perf_if (mem_perf_if),
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`endif
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// Core request
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.core_req_valid (per_cluster_mem_req_valid),
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.core_req_rw (per_cluster_mem_req_rw),
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.core_req_byteen (per_cluster_mem_req_byteen),
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.core_req_addr (per_cluster_mem_req_addr),
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.core_req_data (per_cluster_mem_req_data),
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.core_req_tag (per_cluster_mem_req_tag),
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.core_req_ready (per_cluster_mem_req_ready),
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// Core response
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.core_rsp_valid (per_cluster_mem_rsp_valid),
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.core_rsp_data (per_cluster_mem_rsp_data),
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.core_rsp_tag (per_cluster_mem_rsp_tag),
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.core_rsp_ready (per_cluster_mem_rsp_ready),
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`UNUSED_PIN (core_rsp_tmask),
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// Memory request
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.mem_req_valid (mem_req_valid),
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.mem_req_rw (mem_req_rw),
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.mem_req_byteen (mem_req_byteen),
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.mem_req_addr (mem_req_addr),
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.mem_req_data (mem_req_data),
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.mem_req_tag (mem_req_tag),
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.mem_req_ready (mem_req_ready),
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// Memory response
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.mem_rsp_valid (mem_rsp_valid),
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.mem_rsp_data (mem_rsp_data),
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.mem_rsp_tag (mem_rsp_tag),
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.mem_rsp_ready (mem_rsp_ready)
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);
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end else begin
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`RESET_RELAY (mem_arb_reset);
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VX_mem_arb #(
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.NUM_REQS (`NUM_CLUSTERS),
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.DATA_WIDTH (`L3_MEM_DATA_WIDTH),
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.ADDR_WIDTH (`L3_MEM_ADDR_WIDTH),
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.TAG_IN_WIDTH (`L2_MEM_TAG_WIDTH),
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.TYPE ("R"),
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.BUFFERED_REQ (1),
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.BUFFERED_RSP (1)
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) mem_arb (
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.clk (clk),
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.reset (mem_arb_reset),
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// Core request
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.req_valid_in (per_cluster_mem_req_valid),
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.req_rw_in (per_cluster_mem_req_rw),
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.req_byteen_in (per_cluster_mem_req_byteen),
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.req_addr_in (per_cluster_mem_req_addr),
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.req_data_in (per_cluster_mem_req_data),
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.req_tag_in (per_cluster_mem_req_tag),
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.req_ready_in (per_cluster_mem_req_ready),
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// Memory request
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.req_valid_out (mem_req_valid),
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.req_rw_out (mem_req_rw),
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.req_byteen_out (mem_req_byteen),
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.req_addr_out (mem_req_addr),
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.req_data_out (mem_req_data),
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.req_tag_out (mem_req_tag),
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.req_ready_out (mem_req_ready),
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// Core response
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.rsp_valid_out (per_cluster_mem_rsp_valid),
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.rsp_data_out (per_cluster_mem_rsp_data),
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.rsp_tag_out (per_cluster_mem_rsp_tag),
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.rsp_ready_out (per_cluster_mem_rsp_ready),
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// Memory response
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.rsp_valid_in (mem_rsp_valid),
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.rsp_tag_in (mem_rsp_tag),
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.rsp_data_in (mem_rsp_data),
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.rsp_ready_in (mem_rsp_ready)
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);
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.dcr_bus_if (cluster_dcr_bus_if),
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.mem_bus_if (per_cluster_mem_bus_if[i]),
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.sim_ebreak (per_cluster_sim_ebreak[i]),
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.sim_wb_value (per_cluster_sim_wb_value[i]),
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.busy (per_cluster_busy[i])
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);
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end
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`SCOPE_ASSIGN (reset, reset);
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`SCOPE_ASSIGN (mem_req_fire, mem_req_valid && mem_req_ready);
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`SCOPE_ASSIGN (mem_req_addr, `TO_FULL_ADDR(mem_req_addr));
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`SCOPE_ASSIGN (mem_req_rw, mem_req_rw);
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`SCOPE_ASSIGN (mem_req_byteen, mem_req_byteen);
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`SCOPE_ASSIGN (mem_req_data, mem_req_data);
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`SCOPE_ASSIGN (mem_req_tag, mem_req_tag);
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`SCOPE_ASSIGN (mem_rsp_fire, mem_rsp_valid && mem_rsp_ready);
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`SCOPE_ASSIGN (mem_rsp_data, mem_rsp_data);
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`SCOPE_ASSIGN (mem_rsp_tag, mem_rsp_tag);
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`SCOPE_ASSIGN (busy, busy);
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`BUFFER_BUSY (busy, (| per_cluster_busy), (`NUM_CLUSTERS > 1));
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`ifdef PERF_ENABLE
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reg [`PERF_CTR_BITS-1:0] perf_mem_pending_reads;
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always @(posedge clk) begin
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if (reset) begin
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perf_mem_pending_reads <= '0;
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end else begin
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perf_mem_pending_reads <= $signed(perf_mem_pending_reads) +
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`PERF_CTR_BITS'($signed(2'(mem_req_fire && ~mem_bus_if.req_data.rw) - 2'(mem_rsp_fire)));
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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mem_perf <= '0;
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end else begin
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if (mem_req_fire && ~mem_bus_if.req_data.rw) begin
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mem_perf.reads <= mem_perf.reads + `PERF_CTR_BITS'(1);
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end
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if (mem_req_fire && mem_bus_if.req_data.rw) begin
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mem_perf.writes <= mem_perf.writes + `PERF_CTR_BITS'(1);
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end
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mem_perf.latency <= mem_perf.latency + perf_mem_pending_reads;
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end
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end
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`endif
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`ifdef DBG_TRACE_CORE_MEM
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always @(posedge clk) begin
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if (mem_req_valid && mem_req_ready) begin
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if (mem_req_fire) begin
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if (mem_req_rw)
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dpi_trace("%d: MEM Wr Req: addr=%0h, tag=%0h, byteen=%0h data=%0h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen, mem_req_data);
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`TRACE(1, ("%d: MEM Wr Req: addr=0x%0h, tag=0x%0h, byteen=0x%0h data=0x%0h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen, mem_req_data));
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else
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dpi_trace("%d: MEM Rd Req: addr=%0h, tag=%0h, byteen=%0h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen);
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`TRACE(1, ("%d: MEM Rd Req: addr=0x%0h, tag=0x%0h, byteen=0x%0h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen));
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end
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if (mem_rsp_valid && mem_rsp_ready) begin
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dpi_trace("%d: MEM Rsp: tag=%0h, data=%0h\n", $time, mem_rsp_tag, mem_rsp_data);
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if (mem_rsp_fire) begin
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`TRACE(1, ("%d: MEM Rsp: tag=0x%0h, data=0x%0h\n", $time, mem_rsp_tag, mem_rsp_data));
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end
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end
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`endif
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`ifndef NDEBUG
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`ifdef SIMULATION
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always @(posedge clk) begin
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$fflush(); // flush stdout buffer
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end
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`endif
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endmodule
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endmodule
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