minor update

ci/regression.sh

@@ -140,7 +140,7 @@ echo "stress2 tests done!"
 
 usage()
 {
-    echo "usage: regression [-coverage] [-cluster] [-debug] [-config] [-stress#n] [-all] [-h|--help]"
+    echo "usage: regression [-coverage] [-cluster] [-debug] [-config] [-stress[#n]] [-all] [-h|--help]"
 }
 
 while [ "$1" != "" ]; do
@@ -159,6 +159,10 @@ while [ "$1" != "" ]; do
                 ;;
         -stress2 ) stress2
                 ;;
+        -stress ) stress0
+                  stress1
+                  stress2
+                ;;
         -all ) coverage
                cluster
                debug

hw/rtl/afu/VX_avs_wrapper.v

@@ -69,8 +69,8 @@ module VX_avs_wrapper #(
         ) pending_size (
             .clk   (clk),
             .reset (reset),
-            .push  (avs_reqq_push[i]),
+            .incr  (avs_reqq_push[i]),
-            .pop   (avs_reqq_pop[i]),            
+            .decr  (avs_reqq_pop[i]),            
             .full  (req_queue_going_full[i]),
             .size  (req_queue_size[i]),
             `UNUSED_PIN (empty)

hw/rtl/afu/vortex_afu.sv

@@ -645,8 +645,8 @@ VX_pending_size #(
 ) cci_rd_pending_size (
     .clk   (clk),
     .reset (reset),
-    .push  (cci_rd_req_fire),
+    .incr  (cci_rd_req_fire),
-    .pop   (cci_rdq_pop),
+    .decr  (cci_rdq_pop),
     .full  (cci_pending_reads_full),
     .size  (cci_pending_reads),
     `UNUSED_PIN (empty)
@@ -804,8 +804,8 @@ VX_pending_size #(
 ) cci_wr_pending_size (
     .clk   (clk),
     .reset (reset),
-    .push  (cci_mem_rd_rsp_fire),
+    .incr  (cci_mem_rd_rsp_fire),
-    .pop   (cci_wr_rsp_fire),
+    .decr  (cci_wr_rsp_fire),
     .empty (cci_pending_writes_empty),
     .full  (cci_pending_writes_full),
     .size  (cci_pending_writes)

hw/rtl/cache/VX_core_req_bank_sel.v

@@ -281,22 +281,11 @@ module VX_core_req_bank_sel #(
 `ifdef PERF_ENABLE
     reg [NUM_REQS-1:0] core_req_sel_r;
 
-    if (SHARED_BANK_READY == 0) begin
+    always @(*) begin
-        always @(*) begin
+        core_req_sel_r = 0;
-            core_req_sel_r = 0;
+        for (integer i = 0; i < NUM_REQS; ++i) begin
-            for (integer i = 0; i < NUM_REQS; ++i) begin
+            if (core_req_valid[i]) begin
-                if (core_req_valid[i]) begin
+                core_req_sel_r[i] = per_bank_core_req_ready[core_req_bid[i]];
-                    core_req_sel_r[i] = per_bank_core_req_ready[core_req_bid[i]];
-                end
-            end
-        end
-    end else begin
-        always @(*) begin
-            core_req_sel_r = 0;
-            for (integer i = 0; i < NUM_REQS; ++i) begin
-                if (core_req_valid[i]) begin
-                    core_req_sel_r[i] = per_bank_core_req_ready;
-                end
             end
         end
     end

hw/rtl/libs/VX_index_buffer.v

@@ -42,8 +42,8 @@ module VX_index_buffer #(
         if (release_slot) begin
             free_slots_n[release_addr] = 1;                
         end
-        if (acquire_slot)  begin
+        if (acquire_slot) begin
-             free_slots_n[write_addr_r] = 0;
+            free_slots_n[write_addr_r] = 0;
         end            
     end    
 

hw/rtl/libs/VX_pending_size.v

@@ -7,8 +7,8 @@ module VX_pending_size #(
 ) (
     input wire  clk,
     input wire  reset,
-    input wire  push,
+    input wire  incr,
-    input wire  pop,
+    input wire  decr,
     output wire empty,
     output wire full,
     output wire [SIZEW-1:0] size
@@ -25,19 +25,19 @@ module VX_pending_size #(
             empty_r <= 1;
             full_r  <= 0;
         end else begin
-            assert(!push || !full);
+            assert(!incr || !full);
-            if (push) begin
+            if (incr) begin
-                if (!pop) begin
+                if (!decr) begin
                     empty_r <= 0;
                     if (used_r == ADDRW'(SIZE-1))
                         full_r <= 1;
                 end
-            end else if (pop) begin
+            end else if (decr) begin
                 full_r <= 0;
                 if (used_r == ADDRW'(1))
                     empty_r <= 1;                
             end
-            used_r <= used_r + ADDRW'($signed(2'(push && !pop) - 2'(pop && !push)));
+            used_r <= used_r + ADDRW'($signed(2'(incr && !decr) - 2'(decr && !incr)));
         end
     end