debug tracing refactoring

2021-10-17 13:42:16 -07:00
parent af6d9e7a8b
commit bf72800676
26 changed files with 148 additions and 169 deletions
--- a/hw/rtl/VX_issue.sv
+++ b/hw/rtl/VX_issue.sv
@@ -204,7 +204,7 @@ module VX_issue #(
 `endif
 `endif

-`ifdef DBG_PRINT_PIPELINE
+`ifdef DBG_TRACE_PIPELINE
    always @(posedge clk) begin
        if (alu_req_if.valid && alu_req_if.ready) begin
            dpi_trace("%d: core%0d-issue: wid=%0d, PC=%0h, ex=ALU, tmask=%b, rd=%0d, rs1_data=",