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code refactoring

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This commit is contained in:
Blaise Tine
2020-03-26 01:41:01 -04:00
parent 5372c07b01
commit bf3d1fb5a2
4 changed files with 44 additions and 64 deletions
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2
rtl/Makefile
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@@ -85,4 +85,4 @@ runRel: wRel
(cd obj_dir && ./VVortex) (cd obj_dir && ./VVortex)
clean: clean:
rm obj_dir/* rm -rf obj_dir

4
rtl/VX_define.v
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@@ -127,8 +127,10 @@
`define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS) `define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS)
`define SINGLE_CORE_BENCH 1 //`define SINGLE_CORE_BENCH
`define GLOBAL_BLOCK_SIZE_BYTES 16 `define GLOBAL_BLOCK_SIZE_BYTES 16
// ========================================= Dcache Configurable Knobs ========================================= // ========================================= Dcache Configurable Knobs =========================================
// General Cache Knobs // General Cache Knobs

5
rtl/Vortex.v
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@@ -6,7 +6,6 @@ module Vortex
parameter CORE_ID = 0 parameter CORE_ID = 0
) )
( (
`ifdef SINGLE_CORE_BENCH `ifdef SINGLE_CORE_BENCH
input wire clk, input wire clk,
input wire reset, input wire reset,
@@ -53,10 +52,10 @@ module Vortex
input wire [31:0] I_snp_req_addr, input wire [31:0] I_snp_req_addr,
output wire I_snp_req_delay, output wire I_snp_req_delay,
output wire out_ebreak output wire out_ebreak
`else `else
input wire clk, input wire clk,
input wire reset, input wire reset,
// IO // IO

97
rtl/Vortex_SOC.v
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@@ -3,40 +3,40 @@
module Vortex_SOC ( module Vortex_SOC (
input wire clk, // System Clock
input wire reset, input wire clk,
// IO input wire reset,
output wire io_valid[`NUMBER_CORES-1:0],
output wire[31:0] io_data [`NUMBER_CORES-1:0],
output wire[31:0] number_cores, // IO
output wire io_valid[`NUMBER_CORES-1:0],
output wire[31:0] io_data [`NUMBER_CORES-1:0],
output wire[31:0] number_cores,
// DRAM Dcache Req // DRAM Dcache Req
output wire out_dram_req, output wire out_dram_req,
output wire out_dram_req_write, output wire out_dram_req_write,
output wire out_dram_req_read, output wire out_dram_req_read,
output wire [31:0] out_dram_req_addr, output wire [31:0] out_dram_req_addr,
output wire [31:0] out_dram_req_size, output wire [31:0] out_dram_req_size,
output wire [31:0] out_dram_req_data[`DBANK_LINE_SIZE_RNG], output wire [31:0] out_dram_req_data[`DBANK_LINE_SIZE_RNG],
output wire [31:0] out_dram_expected_lat, output wire [31:0] out_dram_expected_lat,
// DRAM Dcache Res // DRAM Dcache Res
output wire out_dram_fill_accept, output wire out_dram_fill_accept,
input wire out_dram_fill_rsp, input wire out_dram_fill_rsp,
input wire [31:0] out_dram_fill_rsp_addr, input wire [31:0] out_dram_fill_rsp_addr,
input wire [31:0] out_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG], input wire [31:0] out_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
input wire l3c_snp_req, input wire llc_snp_req,
input wire l3c_snp_req_addr, input wire llc_snp_req_addr,
output wire l3c_snp_req_delay, output wire llc_snp_req_delay,
output wire out_ebreak
output wire out_ebreak );
);
`ifdef L3C `ifdef L3C
// DRAM Dcache Req // DRAM Dcache Req
wire [`NUMBER_CLUSTERS-1:0] dram_req; wire [`NUMBER_CLUSTERS-1:0] dram_req;
wire [`NUMBER_CLUSTERS-1:0] dram_req_write; wire [`NUMBER_CLUSTERS-1:0] dram_req_write;
@@ -54,11 +54,7 @@ module Vortex_SOC (
assign number_cores = `NUMBER_CORES; assign number_cores = `NUMBER_CORES;
// IO // Out ebreak
// wire per_core_io_valid[`NUMBER_CORES-1:0];
// wire[31:0] per_core_io_data[`NUMBER_CORES-1:0];
// Out ebreak
wire[`NUMBER_CORES-1:0] per_core_out_ebreak; wire[`NUMBER_CORES-1:0] per_core_out_ebreak;
assign out_ebreak = (&per_core_out_ebreak); assign out_ebreak = (&per_core_out_ebreak);
@@ -71,18 +67,17 @@ module Vortex_SOC (
wire l3c_core_accept; wire l3c_core_accept;
wire l3c_snp_fwd;
wire l3c_snp_fwd; wire[31:0] l3c_snp_fwd_addr;
wire[31:0] l3c_snp_fwd_addr; wire[`L3NUMBER_REQUESTS-1:0] l3c_snp_fwd_delay_temp;
wire[`L3NUMBER_REQUESTS-1:0] l3c_snp_fwd_delay_temp; wire l3c_snp_fwd_delay;
wire l3c_snp_fwd_delay;
assign l3c_snp_fwd_delay = (|l3c_snp_fwd_delay_temp); assign l3c_snp_fwd_delay = (|l3c_snp_fwd_delay_temp);
wire[`L3NUMBER_REQUESTS-1:0] l3c_wb; wire[`L3NUMBER_REQUESTS-1:0] l3c_wb;
wire[`L3NUMBER_REQUESTS-1:0] [31:0] l3c_wb_addr; wire[`L3NUMBER_REQUESTS-1:0] [31:0] l3c_wb_addr;
wire[`L3NUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l3c_wb_data; wire[`L3NUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l3c_wb_data;
wire[`IBANK_LINE_SIZE_RNG][31:0] l3c_dram_req_data; wire[`IBANK_LINE_SIZE_RNG][31:0] l3c_dram_req_data;
wire[`IBANK_LINE_SIZE_RNG][31:0] l3c_dram_fill_rsp_data; wire[`IBANK_LINE_SIZE_RNG][31:0] l3c_dram_fill_rsp_data;
@@ -95,9 +90,6 @@ module Vortex_SOC (
end end
endgenerate endgenerate
// //
genvar l3c_curr_core; genvar l3c_curr_core;
generate generate
@@ -203,9 +195,9 @@ module Vortex_SOC (
.dram_snp_full (dram_snp_full), .dram_snp_full (dram_snp_full),
// Snoop Request // Snoop Request
.snp_req (l3c_snp_req), .snp_req (llc_snp_req),
.snp_req_addr (l3c_snp_req_addr), .snp_req_addr (llc_snp_req_addr),
.snp_req_delay (l3c_snp_req_delay), .snp_req_delay (llc_snp_req_delay),
.snp_fwd (l3c_snp_fwd), .snp_fwd (l3c_snp_fwd),
.snp_fwd_addr (l3c_snp_fwd_addr), .snp_fwd_addr (l3c_snp_fwd_addr),
@@ -227,8 +219,6 @@ module Vortex_SOC (
for (curr_cluster = 0; curr_cluster < `NUMBER_CLUSTERS; curr_cluster=curr_cluster+1) begin for (curr_cluster = 0; curr_cluster < `NUMBER_CLUSTERS; curr_cluster=curr_cluster+1) begin
////////////////////// BEGIN CLUSTER ///////////////// ////////////////////// BEGIN CLUSTER /////////////////
// DRAM Dcache Req // DRAM Dcache Req
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req; wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req_write; wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req_write;
@@ -260,8 +250,6 @@ module Vortex_SOC (
wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_fill_rsp_addr; wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_fill_rsp_addr;
wire[`NUMBER_CORES_PER_CLUSTER-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_fill_rsp_data; wire[`NUMBER_CORES_PER_CLUSTER-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_fill_rsp_data;
// Snoop Requests // Snoop Requests
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dcache_snp_req; wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dcache_snp_req;
wire[`NUMBER_CORES_PER_CLUSTER-1:0][31:0] per_core_dcache_snp_req_addr; wire[`NUMBER_CORES_PER_CLUSTER-1:0][31:0] per_core_dcache_snp_req_addr;
@@ -271,7 +259,6 @@ module Vortex_SOC (
wire[`NUMBER_CORES_PER_CLUSTER-1:0][31:0] per_core_icache_snp_req_addr; wire[`NUMBER_CORES_PER_CLUSTER-1:0][31:0] per_core_icache_snp_req_addr;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_icache_snp_req_delay; wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_icache_snp_req_delay;
// generate // generate
for (curr_core = 0; curr_core < `NUMBER_CORES_PER_CLUSTER; curr_core=curr_core+1) begin for (curr_core = 0; curr_core < `NUMBER_CORES_PER_CLUSTER; curr_core=curr_core+1) begin
@@ -346,8 +333,6 @@ module Vortex_SOC (
// endgenerate // endgenerate
//
// generate // generate
for (l2c_curr_core = 0; l2c_curr_core < `LLNUMBER_REQUESTS; l2c_curr_core=l2c_curr_core+2) begin for (l2c_curr_core = 0; l2c_curr_core < `LLNUMBER_REQUESTS; l2c_curr_core=l2c_curr_core+2) begin
// Core Request // Core Request
@@ -492,7 +477,6 @@ module Vortex_SOC (
`else `else
assign number_cores = `NUMBER_CORES; assign number_cores = `NUMBER_CORES;
// IO // IO
@@ -545,6 +529,7 @@ module Vortex_SOC (
assign io_valid[curr_core] = per_core_io_valid[curr_core]; assign io_valid[curr_core] = per_core_io_valid[curr_core];
assign io_data [curr_core] = per_core_io_data [curr_core]; assign io_data [curr_core] = per_core_io_data [curr_core];
Vortex #(.CORE_ID(curr_core)) vortex_core( Vortex #(.CORE_ID(curr_core)) vortex_core(
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -735,16 +720,10 @@ module Vortex_SOC (
.dram_snp_full (dram_snp_full), .dram_snp_full (dram_snp_full),
// Snoop Request // Snoop Request
.snp_req (l3c_snp_req), .snp_req (llc_snp_req),
.snp_req_addr (l3c_snp_req_addr) .snp_req_addr (llc_snp_req_addr)
); );
//////////////////// L2 Cache ////////////////////
`endif `endif