code refactoring

2020-03-26 01:41:01 -04:00
parent 5372c07b01
commit bf3d1fb5a2
4 changed files with 44 additions and 64 deletions
--- a/rtl/Vortex.v
+++ b/rtl/Vortex.v
@@ -6,7 +6,6 @@ module Vortex
 		parameter CORE_ID = 0
 	)
 	(
-
 		`ifdef SINGLE_CORE_BENCH
 			input  wire           clk,
 			input  wire           reset,
@@ -53,10 +52,10 @@ module Vortex
 		    input  wire [31:0]                       I_snp_req_addr,
 		    output wire                              I_snp_req_delay,

-
-
 		    output wire        out_ebreak
+
 		 `else 
+
 			input  wire           clk,
 			input  wire           reset,
 			// IO