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yosys synthesis refactoring

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This commit is contained in:
Blaise Tine
2020-07-10 18:56:41 -04:00
parent 77c3b2d45f
commit bdfacf709c
28 changed files with 136 additions and 134 deletions
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10
hw/rtl/libs/VX_divide.v
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@@ -10,11 +10,11 @@ module VX_divide #(
input wire clk,
input wire reset,
input [WIDTHN-1:0] numer,
input [WIDTHD-1:0] denom,
input wire [WIDTHN-1:0] numer,
input wire [WIDTHD-1:0] denom,
output reg [WIDTHN-1:0] quotient,
output reg [WIDTHD-1:0] remainder
output wire [WIDTHN-1:0] quotient,
output wire [WIDTHD-1:0] remainder
);
`ifdef QUARTUS
@@ -36,7 +36,7 @@ module VX_divide #(
quartus_div.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED",
quartus_div.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED",
quartus_div.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE",
quartus_div.lpm_pipeline = PIPELINE;
quartus_div.lpm_pipeline = PIPELINE;
`else

11
hw/rtl/libs/VX_encoder_onehot.v
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@@ -3,20 +3,19 @@
module VX_encoder_onehot #(
parameter N = 6
) (
input wire [N-1:0] onehot,
output reg valid,
output reg [`LOG2UP(N)-1:0] value
input wire [N-1:0] onehot,
output reg [`LOG2UP(N)-1:0] binary,
output reg valid
);
integer i;
always @(*) begin
valid = 1'b0;
value = {`LOG2UP(N){1'bx}};
binary = `LOG2UP(N)'(0);
for (i = 0; i < N; i++) begin
if (onehot[i]) begin
valid = 1'b1;
value = `LOG2UP(N)'(i);
break;
binary = `LOG2UP(N)'(i);
end
end
end

2
hw/rtl/libs/VX_fair_arbiter.v
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@@ -1,7 +1,7 @@
`include "VX_define.vh"
module VX_fair_arbiter #(
parameter N = 0
parameter N = 1
) (
input wire clk,
input wire reset,

2
hw/rtl/libs/VX_fixed_arbiter.v
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@@ -1,7 +1,7 @@
`include "VX_define.vh"
module VX_fixed_arbiter #(
parameter N = 0
parameter N = 1
) (
input wire clk,
input wire reset,

4
hw/rtl/libs/VX_generic_queue.v
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@@ -1,7 +1,7 @@
`include "VX_define.vh"
module VX_generic_queue #(
parameter DATAW,
parameter DATAW = 1,
parameter SIZE = 16,
parameter BUFFERED_OUTPUT = 1
) (
@@ -15,7 +15,7 @@ module VX_generic_queue #(
output wire full,
output wire [`LOG2UP(SIZE+1)-1:0] size
);
`STATIC_ASSERT(`ISPOW2(SIZE), "must be 0 or power of 2!");
`STATIC_ASSERT(`ISPOW2(SIZE), "must be 0 or power of 2!")
reg [`LOG2UP(SIZE+1)-1:0] size_r;
wire reading;

2
hw/rtl/libs/VX_generic_register.v
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@@ -1,7 +1,7 @@
`include "VX_define.vh"
module VX_generic_register #(
parameter N,
parameter N = 1,
parameter PASSTHRU = 0
) (
input wire clk,

4
hw/rtl/libs/VX_indexable_queue.v
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@@ -1,8 +1,8 @@
`include "VX_define.vh"
module VX_indexable_queue #(
parameter DATAW,
parameter SIZE
parameter DATAW = 1,
parameter SIZE = 1
) (
input wire clk,
input wire reset,

10
hw/rtl/libs/VX_matrix_arbiter.v
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@@ -1,7 +1,7 @@
`include "VX_define.vh"
module VX_matrix_arbiter #(
parameter N = 0
parameter N = 1
) (
input wire clk,
input wire reset,
@@ -27,8 +27,8 @@ module VX_matrix_arbiter #(
genvar i, j;
for (i = 0; i < N; ++i) begin
for (j = 0; j < N; ++j) begin
for (i = 0; i < N; i++) begin
for (j = 0; j < N; j++) begin
if (j > i) begin
assign pri[j][i] = requests[i] && state[i][j];
end
@@ -43,8 +43,8 @@ module VX_matrix_arbiter #(
assign grant_onehot[i] = requests[i] && !(| pri[i]);
end
for (i = 0; i < N; ++i) begin
for (j = i + 1; j < N; ++j) begin
for (i = 0; i < N; i++) begin
for (j = i + 1; j < N; j++) begin
always @(posedge clk) begin
if (reset) begin
state[i][j] <= 0;

11
hw/rtl/libs/VX_mult.v
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@@ -7,13 +7,12 @@ module VX_mult #(
parameter SIGNED = 0,
parameter PIPELINE = 0
) (
input clk,
input reset,
input wire clk,
input wire reset,
input [WIDTHA-1:0] dataa,
input [WIDTHB-1:0] datab,
output reg [WIDTHP-1:0] result
input wire [WIDTHA-1:0] dataa,
input wire [WIDTHB-1:0] datab,
output wire [WIDTHP-1:0] result
);
`ifdef QUARTUS

2
hw/rtl/libs/VX_priority_encoder.v
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@@ -1,7 +1,7 @@
`include "VX_define.vh"
module VX_priority_encoder #(
parameter N
parameter N = 1
) (
input wire [N-1:0] data_in,
output reg [`LOG2UP(N)-1:0] data_out,

6
hw/rtl/libs/VX_rr_arbiter.v
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@@ -1,7 +1,7 @@
`include "VX_define.vh"
module VX_rr_arbiter #(
parameter N = 0
parameter N = 1
) (
input wire clk,
input wire reset,
@@ -29,9 +29,9 @@ module VX_rr_arbiter #(
integer i, j;
always @(*) begin
for (i = 0; i < N; ++i) begin
for (i = 0; i < N; i++) begin
grant_table[i] = `CLOG2(N)'(i);
for (j = 0; j < N; ++j) begin
for (j = 0; j < N; j++) begin
if (requests[(i+j) % N]) begin
grant_table[i] = `CLOG2(N)'((i+j) % N);
end