yosys synthesis refactoring

2020-07-10 18:56:41 -04:00
parent 77c3b2d45f
commit bdfacf709c
28 changed files with 136 additions and 134 deletions
--- a/hw/rtl/cache/VX_cache_miss_resrv.v
+++ b/hw/rtl/cache/VX_cache_miss_resrv.v
@@ -66,7 +66,7 @@ module VX_cache_miss_resrv #(

    reg [`LOG2UP(MRVQ_SIZE+1)-1:0] size;

-    `STATIC_ASSERT(MRVQ_SIZE > 5, "invalid size");
+    `STATIC_ASSERT(MRVQ_SIZE > 5, "invalid size")

    assign miss_resrv_full = (size == $bits(size)'(MRVQ_SIZE));
    assign miss_resrv_stop = (size  > $bits(size)'(MRVQ_SIZE-5)); // need to add 5 cycles to prevent pipeline lock